Analog Devices ADuCM4050 2025.07.15 ARM Cortex-M4 Microcontroller based device CM4 r0p1 little true true 3 false 8 32 ADC0 Digital Controller for ADC ADC0 0x40007000 0x0 0x400 registers n ADC0_EVT Event 46 ALERT Alert Indication 0x2C 16 read-write n 0x0 0xFFFFFFFF HI0 Channel 0 High alert status 0 1 read-write HI1 Channel 1 High alert status 2 1 read-write HI2 Channel 2 High alert status 4 1 read-write HI3 Channel 3 High alert status 6 1 read-write LO0 Channel 0 Low alert status 1 1 read-write LO1 Channel 1 Low alert status 3 1 read-write LO2 Channel 2 Low alert status 5 1 read-write LO3 Channel 3 Low alert status 7 1 read-write AVG_CFG Averaging Configuration 0x14 16 read-write n 0x4008 0xFFFFFFFF EN To enable averaging on Channels enabled in enable register 15 1 read-write FACTOR Program averaging factor for averaging enabled channels (1-256) 0 8 read-write OS Enable oversampling 14 1 read-write BAT_OUT Battery Monitoring Result 0x50 16 read-write n 0x0 0xFFFFFFFF RESULT Conversion result of battery monitoring is stored here 0 16 read-only CAL_WORD Calibration Word 0x8 16 read-write n 0x40 0xFFFFFFFF VALUE Offset calibration word 0 7 read-write CFG ADC Configuration 0x0 16 read-write n 0x0 0xFFFFFFFF EN To enable ADC subsystem 4 1 read-write FAST_DISCH For fast switchover of Vref from 2.5 V to 1.25 V 9 1 read-write PWRUP Powering up ADC 0 1 read-write REFBUFEN To enable internal reference buffer 2 1 read-write EXT_REF External reference is used 0 BUF_REF Reference buffer is enabled 1 RST Resets internal buffers and registers when high 6 1 read-write SINKEN To enable additional 50 uA sink current capability @1.25 V, 100 uA current capability @2.5 V 7 1 read-write STARTCAL To start a new offset calibration cycle 5 1 read-write TMPEN To power up temperature sensor 8 1 read-write VREFSEL To select Vref as 1.25 V or 2.5 V 1 1 read-write V_2p5 Vref = 2.5 V 0 V_1p25 Vref = 1.25 V 1 VREFVBAT VRef VBAT 3 1 read-write VREFVBAT_DEL VRef VBAT delayed 10 1 read-write CFG1 Reference Buffer Low Power Mode 0xC0 16 read-write n 0x400 0xFFFFFFFF RBUFLP Enable low power mode for reference buffer 0 1 read-write CH0_OUT Conversion Result Channel 0 0x30 16 read-write n 0x0 0xFFFFFFFF RESULT Conversion result of channel 0 is stored here 0 16 read-only CH1_OUT Conversion Result Channel 1 0x34 16 read-write n 0x0 0xFFFFFFFF RESULT Conversion result of channel 1 is stored here 0 16 read-only CH2_OUT Conversion Result Channel 2 0x38 16 read-write n 0x0 0xFFFFFFFF RESULT Conversion result of channel 2 is stored here 0 16 read-only CH3_OUT Conversion Result Channel 3 0x3C 16 read-write n 0x0 0xFFFFFFFF RESULT Conversion result of channel 3 is stored here 0 16 read-only CH4_OUT Conversion Result Channel 4 0x40 16 read-write n 0x0 0xFFFFFFFF RESULT Conversion result of channel 4 is stored here 0 16 read-only CH5_OUT Conversion Result Channel 5 0x44 16 read-write n 0x0 0xFFFFFFFF RESULT Conversion result of channel 5 is stored here 0 16 read-only CH6_OUT Conversion Result Channel 6 0x48 16 read-write n 0x0 0xFFFFFFFF RESULT Conversion result of channel 6 is stored here 0 16 read-only CH7_OUT Conversion Result Channel 7 0x4C 16 read-write n 0x0 0xFFFFFFFF RESULT Conversion result of channel 7 is stored here 0 16 read-only CNV_CFG ADC Conversion Configuration 0xC 16 read-write n 0x0 0xFFFFFFFF AUTOMODE Enable Auto Mode 12 1 read-write BAT Enable Battery Monitoring 8 1 read-write DMAEN Enable DMA Channel 13 1 read-write MULTI Set to start multiple conversions 15 1 read-write SEL To select channel(s) to convert 0 8 read-write SINGLE Set to start single conversion 14 1 read-write TMP To select temperature measurement 1 9 1 read-write TMP2 To select temperature measurement 2 10 1 read-write CNV_TIME ADC Conversion Time 0x10 16 read-write n 0x0 0xFFFFFFFF DLY Delay between two consecutive conversions in terms of number of ACLK cycles 8 8 read-write SAMPTIME Number of clock cycles (ACLK) required for sampling 0 8 read-write DMA_OUT DMA Output Register 0x5C 16 read-write n 0x0 0xFFFFFFFF RESULT Register to store conversion result for DMA 0 16 read-only HYS0 Channel 0 Hysteresis 0x68 16 read-write n 0x0 0xFFFFFFFF EN To enable hysteresis for comparison on Channel 0 15 1 read-write MONCYC Program number of conversion cycles to monitor channel 0 before raising alert 12 3 read-write VALUE Hysteresis value for Channel 0 0 9 read-write HYS1 Channel 1 Hysteresis 0x78 16 read-write n 0x0 0xFFFFFFFF EN To enable hysteresis for comparison on Channel 1 15 1 read-write MONCYC Program number of conversion cycles to monitor channel 1 before raising alert 12 3 read-write VALUE Hysteresis value for Channel 1 0 9 read-write HYS2 Channel 2 Hysteresis 0x88 16 read-write n 0x0 0xFFFFFFFF EN To enable hysteresis for comparison on Channel 2 15 1 read-write MONCYC Program number of conversion cycles to monitor channel 2 before raising alert 12 3 read-write VALUE Hysteresis value for Channel 2 0 9 read-write HYS3 Channel 3 Hysteresis 0x98 16 read-write n 0x0 0xFFFFFFFF EN To enable hysteresis for comparison on Channel 3 15 1 read-write MONCYC Program number of conversion cycles to monitor channel 3 before raising alert 12 3 read-write VALUE Hysteresis value for Channel 3 0 9 read-write IRQ_EN Interrupt Enable 0x20 16 read-write n 0x0 0xFFFFFFFF ALERT Enable Interrupt on Crossing Lower or Higher Limit 12 1 read-write CALDONE Set it to enable interrupt for calibration done 10 1 read-write CNVDONE Set it to enable interrupt after conversion is done 0 1 read-write OVF Set to enable interrupt in case of overflow 11 1 read-write RDY Set to enable interrupt when ADC is ready to convert 13 1 read-write LIM0_HI Channel 0 High Limit 0x64 16 read-write n 0xFFF 0xFFFFFFFF EN To enable high limit comparison on Channel 0 15 1 read-write VALUE High limit value for channel 0 0 12 read-write LIM0_LO Channel 0 Low Limit 0x60 16 read-write n 0x0 0xFFFFFFFF EN To enable low limit comparison on Channel 0 15 1 read-write VALUE Low limit value for channel 0 0 12 read-write LIM1_HI Channel 1 High Limit 0x74 16 read-write n 0xFFF 0xFFFFFFFF EN To enable high limit comparison on Channel 1 15 1 read-write VALUE High limit value for channel 1 0 12 read-write LIM1_LO Channel 1 Low Limit 0x70 16 read-write n 0x0 0xFFFFFFFF EN To enable low limit comparison on Channel 1 15 1 read-write VALUE Low limit value for channel 1 0 12 read-write LIM2_HI Channel 2 High Limit 0x84 16 read-write n 0xFFF 0xFFFFFFFF EN To enable high limit comparison on Channel 2 15 1 read-write VALUE High limit value for channel 2 0 12 read-write LIM2_LO Channel 2 Low Limit 0x80 16 read-write n 0x0 0xFFFFFFFF EN To enable low limit comparison on Channel 2 15 1 read-write VALUE Low limit value for channel 2 0 12 read-write LIM3_HI Channel 3 High Limit 0x94 16 read-write n 0xFFF 0xFFFFFFFF EN To enable high limit comparison on Channel 3 15 1 read-write VALUE High limit value for channel 3 0 12 read-write LIM3_LO Channel 3 Low Limit 0x90 16 read-write n 0x0 0xFFFFFFFF EN To enable low limit comparison on Channel 3 15 1 read-write VALUE Low limit value for channel 3 0 12 read-write OVF Overflow of Output Registers 0x28 16 read-write n 0x0 0xFFFFFFFF BAT Indicates overflow in battery monitoring output register 8 1 read-write CH0 Indicates overflow in channel 0 output register 0 1 read-write CH1 Indicates overflow in channel 1 output register 1 1 read-write CH2 Indicates overflow in channel 2 output register 2 1 read-write CH3 Indicates overflow in channel 3 output register 3 1 read-write CH4 Indicates overflow in channel 4 output register 4 1 read-write CH5 Indicates overflow in channel 5 output register 5 1 read-write CH6 Indicates overflow in channel 6 output register 6 1 read-write CH7 Indicates overflow in channel 7 output register 7 1 read-write TMP Indicates overflow in temperature output register 9 1 read-write TMP2 Indicates overflow in temperature 2 output register 10 1 read-write PWRUP ADC Power-up Time 0x4 16 read-write n 0x41C 0xFFFFFFFF WAIT Program this count to generate 20us wait time with respect to the PCLK frequency 0 11 read-write STAT ADC Status 0x24 16 read-write n 0x0 0xFFFFFFFF BATDONE Indicates conversion done for battery monitoring 8 1 read-write CALDONE Indicates calibration is done 14 1 read-write DONE0 Indicates conversion done on Channel 0 0 1 read-write DONE1 Indicates conversion done on Channel 1 1 1 read-write DONE2 Indicates conversion done on Channel 2 2 1 read-write DONE3 Indicates conversion done on Channel 3 3 1 read-write DONE4 Indicates conversion done on Channel 4 4 1 read-write DONE5 Indicates conversion done on Channel 5 5 1 read-write DONE6 Indicates conversion done on Channel 6 6 1 read-write DONE7 Indicates conversion done on Channel 7 7 1 read-write RDY Indicates ADC is ready to start converting, when using external reference buffer 15 1 read-write TMP2DONE Indicates conversion is done for temperature sensing 2 10 1 read-write TMPDONE Indicates conversion is done for temperature sensing 9 1 read-write TMP2_OUT Temperature Result 2 0x58 16 read-write n 0x0 0xFFFFFFFF RESULT Conversion result of Temperature measurement 2 is stored here 0 16 read-only TMP_OUT Temperature Result 0x54 16 read-write n 0x0 0xFFFFFFFF RESULT Conversion result of Temperature measurement 1 is stored here 0 16 read-only BEEP0 Beeper Driver BEEP0 0x40005C00 0x0 0x100 registers n BEEP_EVT Event 45 CFG Beeper Configuration 0x0 16 read-write n 0x0 0xFFFFFFFF AENDIRQ Tone A End IRQ 11 1 read-write ASTARTIRQ Tone A Start IRQ 10 1 read-write BENDIRQ Tone B End IRQ 13 1 read-write BSTARTIRQ Tone B Start IRQ 12 1 read-write EN Beeper Enable 8 1 write-only SEQATENDIRQ Sequence End IRQ 15 1 read-write SEQNEARENDIRQ Sequence 1 Cycle from End IRQ 14 1 read-write SEQREPEAT Beeper Sequence Repeat Value 0 8 read-write STAT Beeper Status 0x4 16 read-write n 0x0 0xFFFFFFFF AENDED Tone A Has Ended 11 1 read-write ASTARTED Tone A Has Started 10 1 read-write BENDED Tone B Has Ended 13 1 read-write BSTARTED Tone B Has Started 12 1 read-write BUSY Beeper is Busy 8 1 read-only SEQENDED Sequencer Has Ended 15 1 read-write SEQNEAREND Sequencer Last Tone-pair Has Started 14 1 read-write SEQREMAIN Remaining Tone-pair Iterations to Play in Sequence Mode 0 8 read-only TONEA Tone A Data 0x8 16 read-write n 0x1 0xFFFFFFFF DIS Output Disable 15 1 read-write DUR Tone Duration 0 8 read-write FREQ Tone Frequency 8 7 read-write TONEB Tone B Data 0xC 16 read-write n 0x1 0xFFFFFFFF DIS Output Disable 15 1 read-write DUR Tone Duration 0 8 read-write FREQ Tone Frequency 8 7 read-write BUSM0 Bus matrix BUSM0 0x4004C800 0x0 0x50 registers n ARBIT0 Arbitration Priority Configuration for FLASH and SRAM0 0x0 32 read-write n 0x240024 0xFFFFFFFF FLSH_DCODE Flash priority for DCODE 0 2 read-write FLSH_DMA0 Flash priority for DMA0 4 2 read-write FLSH_SBUS Flash priority for SBUS 2 2 read-write SRAM0_DCODE SRAM0 priority for Dcode 16 2 read-write SRAM0_DMA0 SRAM0 priority for DMA0 20 2 read-write SRAM0_SBUS SRAM0 priority for SBUS 18 2 read-write ARBIT1 Arbitration Priority Configuration for SRAM1 0x4 32 read-write n 0x240024 0xFFFFFFFF SRAM1_DCODE SRAM1 priority for Dcode 0 2 read-write SRAM1_DMA0 SRAM1 priority for DMA0 4 2 read-write SRAM1_SBUS SRAM1 priority for SBUS 2 2 read-write ARBIT2 Arbitration Priority Configuration for APB32 and APB16 0x8 32 read-write n 0x240024 0xFFFFFFFF APB16_DCODE APB16 priority for DCODE 16 2 read-write APB16_DMA0 APB16 priority for DMA0 20 2 read-write APB16_SBUS APB16 priority for SBUS 18 2 read-write APB32_DCODE APB32 priority for DCODE 0 2 read-write APB32_DMA0 APB32 priority for DMA0 4 2 read-write APB32_SBUS APB32 priority for SBUS 2 2 read-write ARBIT3 Arbitration Priority Configuration for APB16 priority for core and for DMA1 0xC 32 read-write n 0x10002 0xFFFFFFFF APB16_4DMA_CORE APB16 for dma priority for CORE 16 1 read-write APB16_4DMA_DMA1 APB16 for dma priority for DMA1 17 1 read-write APB16_CORE APB16 priority for CORE 0 1 read-write APB16_DMA1 APB16 priority for DMA1 1 1 read-write ARBIT4 Arbitration Priority Configuration for SRAM1 and SIP 0x14 32 read-write n 0x24 0xFFFFFFFF SRAM2_DCODE SRAM2 priority for Dcode 0 2 read-write SRAM2_DMA0 SRAM2 priority for DMA0 4 2 read-write SRAM2_SBUS SRAM2 priority for SBUS 2 2 read-write CLKG0_CLK Clocking CLKG0_CLK 0x4004C300 0x0 0x50 registers n CTL0 Misc Clock Settings 0x0 32 read-write n 0x78 0xFFFFFFFF CLKMUX Clock mux select 0 2 read-write CLKOUT GPIO clock out select 3 4 read-write HFXTALIE High frequency crystal interrupt enable 15 1 read-write LFXTALIE Low frequency crystal interrupt enable 14 1 read-write PLL_IPSEL SPLL source select mux 11 2 read-write PLL_HFOSC Internal HF oscillator is selected 0 PLL_HFXTAL External HF XTAL oscillator is selected 1 PLL_GPIO GPIO_CLK input is selected 2 PLL_GPIO1 GPIO_CLK input is selected 3 RCLKMUX Flash reference clock and HPBUCK clock source mux 8 2 read-write CTL1 Clock Dividers 0x4 32 read-write n 0x100404 0xFFFFFFFF ACLKDIVCNT ACLK Divide Count 16 9 read-write HCLKDIVCNT HCLK divide count 0 6 read-write PCLKDIVCNT PCLK divide count 8 6 read-write CTL2 HF Oscillator Divided Clock Select 0x8 32 read-write n 0x0 0xFFFFFFFF HFOSCAUTODIV_EN HF Oscillator auto divide by one clock selection during wakeup from Flexi power mode 0 1 read-write HFOSCDIVCLKSEL HF Oscillator divided clock select 1 3 read-write CTL3 System PLL 0xC 32 read-write n 0x681A 0xFFFFFFFF SPLLDIV2 System PLL division by 2 8 1 read-write SPLLEN System PLL enable 9 1 read-write SPLLIE System PLL interrupt enable 10 1 read-write SPLLMSEL System PLL M Divider 11 4 read-write SPLLMUL2 System PLL multiply by 2 16 1 read-write SPLLNSEL System PLL N multiplier 0 5 read-write CTL5 User Clock Gating Control 0x14 32 read-write n 0x5F 0xFFFFFFFF GPIOCLKOFF GPIO clock control 4 1 read-write GPTCLK0OFF GP Timer 0 user control 0 1 read-write GPTCLK1OFF GP Timer 1 user control 1 1 read-write GPTCLK2OFF GP Timer 2 user control 2 1 read-write PERCLKOFF This bit is used to disable all clocks connected to all peripherals 5 1 read-write TMRRGBCLKOFF Timer RGB user control 6 1 read-write UCLKI2COFF I2C clock user control 3 1 read-write STAT0 Clocking Status 0x18 32 read-write n 0x0 0xFFFFFFFF HFXTAL HF crystal status 12 1 read-only HFXTALNOK HF crystal not stable 14 1 read-write HFXTALOK HF crystal stable 13 1 read-write LFXTAL LF crystal status 8 1 read-only LFXTALNOK LF crystal not stable 10 1 read-write LFXTALOK LF crystal stable 9 1 read-write SPLL System PLL status 0 1 read-only SPLLLK System PLL lock 1 1 read-write SPLLUNLK System PLL unlock 2 1 read-write CLKG0_OSC Clocking CLKG0_OSC 0x4004C100 0x0 0x50 registers n CLKG_XTAL_OSC_EVT Crystal Oscillator Event 41 CLKG_PLL_EVT PLL Event 43 CLKG_ROOTCLK_ERR Root Clock Error 71 CTL Oscillator Control 0x10 32 read-write n 0x60002 0xFFFFFFFF HFOSC_EN High frequency internal oscillator enable 1 1 read-write HFOSC_OK Status of HFOSC oscillator 9 1 read-only HFX_EN High frequency crystal oscillator enable 3 1 read-write HFX_OK Status of HFXTAL oscillator 11 1 read-only LFCLK_MUX 32 kHz clock select mux 0 1 read-write LFOSC_OK Status of LFOSC oscillator 8 1 read-only LFX_AUTSW_EN Enables automatic Switching of the LF Mux to LFOSC on LFXTAL Failure 12 1 read-write LFX_AUTSW_STA Status of automatic switching of the LF Mux to LFOSC upon detection of LFXTAL failure 13 1 read-write LFX_BYP Low frequency crystal oscillator Bypass 4 1 read-write LFX_EN Low frequency crystal oscillator enable 2 1 read-write LFX_FAIL_STA LF XTAL (crystal clock) Not Stable 31 1 read-write LFX_MON_EN LFXTAL clock monitor and Clock FAIL interrupt enable 5 1 read-write LFX_OK Status of LFXTAL oscillator 10 1 read-only LFX_ROBUST_EN LFXTAL Mode select 14 1 read-write LFX_ROBUST_LD LFXTAL Robust Mode Load select 15 2 read-write ROOT_AUTSW_EN Enables automatic Switching of the Root clock to HFOSC on Root clock Failure 21 1 read-write ROOT_AUTSW_STA Status of automatic switching of the Root clock to HFOSC upon detection of Root clock failure 22 1 read-write ROOT_FAIL_STA Root clock (crystal clock) Not Stable 30 1 read-write ROOT_MON_EN ROOT clock monitor and Clock FAIL interrupt enable 20 1 read-write KEY Key Protection for OSCCTRL 0xC 32 read-write n 0x0 0xFFFFFFFF VALUE Oscillator key 0 16 write-only CRC0 CRC Accelerator CRC0 0x40040000 0x0 0x100 registers n CTL CRC Control 0x0 32 read-write n 0x10000000 0xFFFFFFFF BITMIRR Bit Mirroring 2 1 read-write BITMIRR_DIS Bit Mirroring is disabled 0 BITMIRR_EN Bit Mirroring is enabled 1 BYTMIRR Byte Mirroring 3 1 read-write BYTEMIR_DIS Byte Mirroring is disabled 0 BYTEMIR_EN Byte Mirroring is enabled 1 EN CRC Peripheral Enable 0 1 read-write CRC_DIS CRC peripheral is disabled 0 CRC_EN CRC peripheral is enabled 1 LSBFIRST LSB First Calculation Order 1 1 read-write MSB_FIRST MSB First CRC calculation is done 0 LSB_FIRST LSB First CRC calculation is done 1 RevID Revision ID 28 4 read-only W16SWP Word16 Swap 4 1 read-write W16SP_DIS Word16 Swap disabled 0 W16SP_EN Word16 Swap enabled 1 IPBITS0 Input Data Bits 0x10 8 read-write n 0x0 0xFFFFFFFF DATA_BITS Input Data Bits 0 8 write-only IPBITS1 Input Data Bits 0x11 8 read-write n 0x0 0xFFFFFFFF DATA_BITS Input Data Bits 0 8 write-only IPBITS2 Input Data Bits 0x12 8 read-write n 0x0 0xFFFFFFFF DATA_BITS Input Data Bits 0 8 write-only IPBITS3 Input Data Bits 0x13 8 read-write n 0x0 0xFFFFFFFF DATA_BITS Input Data Bits 0 8 write-only IPBITS4 Input Data Bits 0x14 8 read-write n 0x0 0xFFFFFFFF DATA_BITS Input Data Bits 0 8 write-only IPBITS5 Input Data Bits 0x15 8 read-write n 0x0 0xFFFFFFFF DATA_BITS Input Data Bits 0 8 write-only IPBITS6 Input Data Bits 0x16 8 read-write n 0x0 0xFFFFFFFF DATA_BITS Input Data Bits 0 8 write-only IPBITS7 Input Data Bits 0x17 8 read-write n 0x0 0xFFFFFFFF DATA_BITS Input Data Bits 0 8 write-only IPBITS[0] Input Data Bits 0x20 8 read-write n 0x0 0xFFFFFFFF DATA_BITS Input Data Bits 0 8 write-only IPBITS[1] Input Data Bits 0x31 8 read-write n 0x0 0xFFFFFFFF DATA_BITS Input Data Bits 0 8 write-only IPBITS[2] Input Data Bits 0x43 8 read-write n 0x0 0xFFFFFFFF DATA_BITS Input Data Bits 0 8 write-only IPBITS[3] Input Data Bits 0x56 8 read-write n 0x0 0xFFFFFFFF DATA_BITS Input Data Bits 0 8 write-only IPBITS[4] Input Data Bits 0x6A 8 read-write n 0x0 0xFFFFFFFF DATA_BITS Input Data Bits 0 8 write-only IPBITS[5] Input Data Bits 0x7F 8 read-write n 0x0 0xFFFFFFFF DATA_BITS Input Data Bits 0 8 write-only IPBITS[6] Input Data Bits 0x95 8 read-write n 0x0 0xFFFFFFFF DATA_BITS Input Data Bits 0 8 write-only IPBITS[7] Input Data Bits 0xAC 8 read-write n 0x0 0xFFFFFFFF DATA_BITS Input Data Bits 0 8 write-only IPBYTE Input Data Byte IPBITS0 0x10 8 read-write n 0x0 0xFFFFFFFF DATA_BYTE Input Data Byte 0 8 write-only IPDATA Input Data Word 0x4 32 read-write n 0x0 0xFFFFFFFF VALUE Data Input 0 32 write-only POLY Programmable CRC Polynomial 0xC 32 read-write n 0x4C11DB7 0xFFFFFFFF VALUE CRC Reduction Polynomial 0 32 read-write RESULT CRC Result 0x8 32 read-write n 0x0 0xFFFFFFFF VALUE CRC Residue 0 32 read-write CRYPT0 Register Map for the Crypto Block CRYPT0 0x40044000 0x0 0x200 registers n CRYPT_EVT Event 38 AESKEY0 AES Key Bits [31:0] 0x2C 32 read-write n 0x0 0xFFFFFFFF VALUE Key: Bytes [3:0] 0 32 write-only AESKEY1 AES Key Bits [63:32] 0x30 32 read-write n 0x0 0xFFFFFFFF VALUE Key: Bytes [7:4] 0 32 write-only AESKEY2 AES Key Bits [95:64] 0x34 32 read-write n 0x0 0xFFFFFFFF VALUE Key: Bytes [11:8] 0 32 write-only AESKEY3 AES Key Bits [127:96] 0x38 32 read-write n 0x0 0xFFFFFFFF VALUE Key: Bytes [15:12] 0 32 write-only AESKEY4 AES Key Bits [159:128] 0x3C 32 read-write n 0x0 0xFFFFFFFF VALUE Key: Bytes [19:16] 0 32 write-only AESKEY5 AES Key Bits [191:160] 0x40 32 read-write n 0x0 0xFFFFFFFF VALUE Key: Bytes [23:20] 0 32 write-only AESKEY6 AES Key Bits [223:192] 0x44 32 read-write n 0x0 0xFFFFFFFF VALUE Key: Bytes [27:24] 0 32 write-only AESKEY7 AES Key Bits [255:224] 0x48 32 read-write n 0x0 0xFFFFFFFF VALUE Key: Bytes [31:28] 0 32 write-only CCM_NUM_VALID_BYTES NUM_VALID_BYTES 0x74 32 read-write n 0x0 0xFFFFFFFF NUM_VALID_BYTES Number of Valid Bytes in CCM Last Data 0 4 read-write CFG Configuration Register 0x0 32 read-write n 0x20000000 0xFFFFFFFF AESKEYLEN Select Key Length for AES Cipher 8 2 read-write AESKEYLEN128 Uses 128-bit long key 0 AESKEYLEN256 Uses 256-bit long key 2 AES_BYTESWAP Byteswap for AES Input 12 1 read-write BLKEN Enable Bit for Crypto Block 0 1 read-write Enable Enable Crypto Block 0 Disable Disable Crypto Block 1 CBCEN Enable CBC Mode Operation 18 1 read-write CCMEN Enable CCM/CCM* Mode Operation 19 1 read-write CMACEN Enable CMAC Mode Operation 20 1 read-write CTREN Enable CTR Mode Operation 17 1 read-write ECBEN Enable ECB Mode Operation 16 1 read-write ENCR Encrypt or Decrypt 1 1 read-write HMACEN HMAC Enable 21 1 read-write INDMAEN Enable DMA Channel Request for Input Buffer 2 1 read-write DMA_DISABLE_INBUF Disable DMA Requesting for Input Buffer 0 DMA_ENABLE_INBUF Enable DMA Requesting for Input Buffer 1 INFLUSH Input Buffer Flush 4 1 write-only KEY_BYTESWAP Use Key Unwrap Before HMAC 14 1 read-write KUWKeyLen Key Length Key Wrap Unwrap 10 2 read-write LEN128 The key size of KUW key is 128 bits 1 LEN256 The key size of KUW key is 256 bits 2 LEN512 The key size of KUW key is 512 bits 3 OUTDMAEN Enable DMA Channel Request for Output Buffer 3 1 read-write DMA_DISABLE_OUTBUF Disable DMA Requesting for Output Buffer 0 DMA_ENABLE_OUTBUF Enable DMA Requesting for Output Buffer 1 OUTFLUSH Output Buffer Flush 5 1 write-only PRKSTOREN Enable PRKSTOR Commands 15 1 read-write RevID Rev ID for Crypto 28 4 read-only SHA256EN Enable SHA-256 Operation 25 1 read-write SHAINIT Restarts SHA Computation 26 1 read-write SHA_BYTESWAP Enable Key Wrap 13 1 read-write CNTRINIT Counter Initialization Vector 0x4C 32 read-write n 0x0 0xFFFFFFFF VALUE Counter Initialization Value 0 20 read-write DATALEN Payload Data Length 0x4 32 read-write n 0x0 0xFFFFFFFF VALUE Length of Payload Data 0 20 read-write INBUF Input Buffer 0x14 32 read-write n 0x0 0xFFFFFFFF VALUE Input Buffer 0 32 write-only INTEN Interrupt Enable Register 0xC 32 read-write n 0x0 0xFFFFFFFF HMACDONEEN Interrupt Enable for HMAC Done 6 1 read-write HMACMSGRDYEN Status Bit for HMAC Message Input Ready 7 1 read-write INOVREN Enable Input Overflow Interrupt 2 1 read-write INRDYEN Enable Input Ready Interrupt 0 1 read-write OUTRDYEN Enables the Output Ready Interrupt 1 1 read-write PRKSTRCMDONEEN PRKSTOR CMD DONE INTEN 8 1 read-write SHADONEN Enable SHA_Done Interrupt 5 1 read-write KUW0 Key Wrap Unwrap Register 0 0x80 32 read-write n 0x0 0xFFFFFFFF KUW0 KUW [31:0] 0 32 write-only KUW1 Key Wrap Unwrap Register 1 0x84 32 read-write n 0x0 0xFFFFFFFF KUW1 KUW [63:32] 0 32 write-only KUW10 Key Wrap Unwrap Register 10 0xA8 32 read-write n 0x0 0xFFFFFFFF KUW10 KUW [351:320] 0 32 write-only KUW11 Key Wrap Unwrap Register 11 0xAC 32 read-write n 0x0 0xFFFFFFFF KUW11 KUW [383:352] 0 32 write-only KUW12 Key Wrap Unwrap Register 12 0xB0 32 read-write n 0x0 0xFFFFFFFF KUW12 KUW [415:384] 0 32 write-only KUW13 Key Wrap Unwrap Register 13 0xB4 32 read-write n 0x0 0xFFFFFFFF KUW13 KUW [447:416] 0 32 write-only KUW14 Key Wrap Unwrap Register 14 0xB8 32 read-write n 0x0 0xFFFFFFFF KUW14 KUW [479:448] 0 32 write-only KUW15 Key Wrap Unwrap Register 15 0xBC 32 read-write n 0x0 0xFFFFFFFF KUW15 KUW [511:480] 0 32 write-only KUW2 Key Wrap Unwrap Register 2 0x88 32 read-write n 0x0 0xFFFFFFFF KUW2 KUW [95:64] 0 32 write-only KUW3 Key Wrap Unwrap Register 3 0x8C 32 read-write n 0x0 0xFFFFFFFF KUW3 KUW [127:96] 0 32 write-only KUW4 Key Wrap Unwrap Register 4 0x90 32 read-write n 0x0 0xFFFFFFFF KUW4 KUW [159:128] 0 32 write-only KUW5 Key Wrap Unwrap Register 5 0x94 32 read-write n 0x0 0xFFFFFFFF KUW5 KUW [191:160] 0 32 write-only KUW6 Key Wrap Unwrap Register 6 0x98 32 read-write n 0x0 0xFFFFFFFF KUW6 KUW [223:192] 0 32 write-only KUW7 Key Wrap Unwrap Register 7 0x9C 32 read-write n 0x0 0xFFFFFFFF KUW7 KUW [255:224] 0 32 write-only KUW8 Key Wrap Unwrap Register 8 0xA0 32 read-write n 0x0 0xFFFFFFFF KUW8 KUW [287:256] 0 32 write-only KUW9 Key Wrap Unwrap Register 9 0xA4 32 read-write n 0x0 0xFFFFFFFF KUW9 KUW [319:288] 0 32 write-only KUWValStr1 Key Wrap Unwrap Validation String [63:32] 0xC0 32 read-write n 0xA6A6A6A6 0xFFFFFFFF InitialValue0 Initial Value 0 32 write-only KUWValStr2 Key Wrap Unwrap Validation String [31:0] 0xC4 32 read-write n 0xA6A6A6A6 0xFFFFFFFF InitialValue1 Initial Value 0 32 write-only NONCE0 Nonce Bits [31:0] 0x1C 32 read-write n 0x0 0xFFFFFFFF VALUE Word 0: Nonce Bits [31:0] 0 32 read-write NONCE1 Nonce Bits [63:32] 0x20 32 read-write n 0x0 0xFFFFFFFF VALUE Word 1: Nonce Bits [63:32] 0 32 read-write NONCE2 Nonce Bits [95:64] 0x24 32 read-write n 0x0 0xFFFFFFFF VALUE Word 2: Nonce Bits [95:64] 0 32 read-write NONCE3 Nonce Bits [127:96] 0x28 32 read-write n 0x0 0xFFFFFFFF VALUE Word 3: Nonce Bits [127:96] 0 32 read-write OUTBUF Output Buffer 0x18 32 read-write n 0x0 0xFFFFFFFF VALUE Output Buffer 0 32 read-only PREFIXLEN Authentication Data Length 0x8 32 read-write n 0x0 0xFFFFFFFF VALUE Length of Associated Data 0 16 read-write PRKSTORCFG PRKSTOR Configuration 0x78 32 read-write n 0x0 0xFFFFFFFF CMD Command Input for PRKSTOR 7 4 read-write KEY_INDEX Index of Key in PRKSTOR 0 7 read-write SHAH0 SHA Bits [31:0] 0x50 32 read-write n 0x6A09E667 0xFFFFFFFF SHAHASH0 Word 0: SHA Hash 0 32 read-only SHAH1 SHA Bits [63:32] 0x54 32 read-write n 0xBB67AE85 0xFFFFFFFF SHAHASH1 Word 1: SHA Hash 0 32 read-only SHAH2 SHA Bits [95:64] 0x58 32 read-write n 0x3C6EF372 0xFFFFFFFF SHAHASH2 Word 2: SHA Hash 0 32 read-only SHAH3 SHA Bits [127:96] 0x5C 32 read-write n 0xA54FF53A 0xFFFFFFFF SHAHASH3 Word 3: SHA Hash 0 32 read-only SHAH4 SHA Bits [159:128] 0x60 32 read-write n 0x510E527F 0xFFFFFFFF SHAHASH4 Word 4: SHA Hash 0 32 read-only SHAH5 SHA Bits [191:160] 0x64 32 read-write n 0x9B05688C 0xFFFFFFFF SHAHASH5 Word 5: SHA Hash 0 32 read-only SHAH6 SHA Bits [223:192] 0x68 32 read-write n 0x1F83D9AB 0xFFFFFFFF SHAHASH6 Word 6: SHA Hash 0 32 read-only SHAH7 SHA Bits [255:224] 0x6C 32 read-write n 0x5BE0CD19 0xFFFFFFFF SHAHASH7 Word 7: SHA Hash 0 32 read-only SHA_LAST_WORD SHA Last Word and Valid Bits Information 0x70 32 read-write n 0x0 0xFFFFFFFF O_Bits_Valid Bits Valid in SHA Last Word Input 1 5 read-write O_Last_Word Last SHA Input Word 0 1 read-write STAT Status Register 0x10 32 read-write n 0x1 0xFFFFFFFF CMD_ISSUED Last Command Issued to PrKStor 27 4 read-only HMACBUSY Status Bit Indicates HMAC Busy 13 1 read-only HMACDONE Status Bit Indicates HMAC Done 14 1 read-write HMACMSGRDY Status Bit Indicates HMAC is Message Ready 15 1 read-write INOVR Overflow in the Input Buffer 2 1 read-write INRDY Input Buffer Status 0 1 read-only INWORDS Number of Words in the Input Buffer 7 3 read-only OUTRDY Output Data Ready 1 1 read-only OUTWORDS Number of Words in the Output Buffer 10 3 read-only PRKSTOR_BUSY Indicates PrKSTOR is Busy 31 1 read-only PRKSTOR_CMD_DONE Indicates Command Done for PrKStor 23 1 read-write PRKSTOR_CMD_FAIL Indicates Last Command Issued Failed 24 1 read-write PRKSTOR_RET_STATUS ECC Errors in the PRKSTOR_RETRIEVE Command 25 2 read-only SHABUSY SHA Busy. in Computation 6 1 read-only SHADONE SHA Computation Complete 5 1 read-write DMA0 DMA DMA0 0x40010000 0x0 0x1000 registers n DMA_CHAN_ERR Channel Error 19 DMA0_CH0_DONE Channel 0 Done 20 DMA0_CH1_DONE Channel 1 Done 21 DMA0_CH2_DONE Channel 2 Done 22 DMA0_CH3_DONE Channel 3 Done 23 DMA0_CH4_DONE Channel 4 Done 24 DMA0_CH5_DONE Channel 5 Done 25 DMA0_CH6_DONE Channel 6 Done 26 DMA0_CH7_DONE Channel 7 Done 27 DMA0_CH8_DONE Channel 8 Done 28 DMA0_CH9_DONE Channel 9 Done 29 DMA0_CH10_DONE Channel 10 Done 30 DMA0_CH11_DONE Channel 11 Done 31 DMA0_CH12_DONE Channel 12 Done 32 DMA0_CH13_DONE Channel 13 Done 33 DMA0_CH14_DONE Channel 14 Done 34 DMA0_CH15_DONE Channel 15 Done 35 DMA0_CH24_DONE Channel 24 Done 39 DMA0_CH16_DONE Channel 16 Done 56 DMA0_CH17_DONE Channel 17 Done 57 DMA0_CH18_DONE Channel 18 Done 58 DMA0_CH19_DONE Channel 19 Done 59 DMA0_CH20_DONE Channel 20 Done 60 DMA0_CH21_DONE Channel 21 Done 61 DMA0_CH22_DONE Channel 22 Done 62 DMA0_CH23_DONE Channel 23 Done 63 DMA0_CH25_DONE Channel 25 Done 67 DMA0_CH26_DONE Channel 26 Done 68 ADBPTR DMA Channel Alternate Control Database Pointer 0xC 32 read-write n 0x200 0xFFFFFFFF ADDR Base Address of the Alternate Data Structure 0 32 read-only ALT_CLR DMA Channel Primary Alternate Clear 0x34 32 read-write n 0x0 0xFFFFFFFF CHAN Select Primary Data Structure 0 27 write-only ALT_SET DMA Channel Primary Alternate Set 0x30 32 read-write n 0x0 0xFFFFFFFF CHAN Control Structure Status / Select Alternate Structure 0 27 read-write BS_CLR DMA Channel Bytes Swap Enable Clear 0x804 32 read-write n 0x0 0xFFFFFFFF CHAN Disable Byte Swap 0 27 write-only BS_SET DMA Channel Bytes Swap Enable Set 0x800 32 read-write n 0x0 0xFFFFFFFF CHAN Byte Swap Status 0 27 read-write CFG DMA Configuration 0x4 32 read-write n 0x0 0xFFFFFFFF MEN Controller Enable 0 1 write-only DSTADDR_CLR DMA Channel Destination Address Decrement Enable Clear 0x81C 32 read-write n 0x0 0xFFFFFFFF CHAN Disable Destination Address Decrement 0 27 write-only DSTADDR_SET DMA Channel Destination Address Decrement Enable Set 0x818 32 read-write n 0x0 0xFFFFFFFF CHAN Destination Address Decrement Status 0 27 read-write EN_CLR DMA Channel Enable Clear 0x2C 32 read-write n 0x0 0xFFFFFFFF CHAN Disable DMA Channels 0 27 write-only EN_SET DMA Channel Enable Set 0x28 32 read-write n 0x0 0xFFFFFFFF CHAN Enable DMA Channels 0 27 read-write ERRCHNL_CLR DMA per Channel Error Clear 0x48 32 read-write n 0x0 0xFFFFFFFF CHAN Per Channel Bus Error Status/Clear 0 27 read-write ERR_CLR DMA Bus Error Clear 0x4C 32 read-write n 0x0 0xFFFFFFFF CHAN Bus Error Status 0 27 read-write INVALIDDESC_CLR DMA per Channel Invalid Descriptor Clear 0x50 32 read-write n 0x0 0xFFFFFFFF CHAN Per Channel Invalid Descriptor Status/Clear 0 27 read-write PDBPTR DMA Channel Primary Control Database Pointer 0x8 32 read-write n 0x0 0xFFFFFFFF ADDR Pointer to the Base Address of the Primary Data Structure 0 32 read-write PRI_CLR DMA Channel Priority Clear 0x3C 32 read-write n 0x0 0xFFFFFFFF CHPRICLR Configure Channel for Default Priority Level 0 27 write-only PRI_SET DMA Channel Priority Set 0x38 32 read-write n 0x0 0xFFFFFFFF CHAN Configure Channel for High Priority 0 27 write-only REVID DMA Controller Revision ID 0xFE0 32 read-write n 0x2 0xFFFFFFFF VALUE DMA Controller Revision ID 0 8 read-only RMSK_CLR DMA Channel Request Mask Clear 0x24 32 read-write n 0x0 0xFFFFFFFF CHAN Clear Request Mask Set Bits 0 27 write-only RMSK_SET DMA Channel Request Mask Set 0x20 32 read-write n 0x0 0xFFFFFFFF CHAN Mask Requests from DMA Channels 0 27 read-write SRCADDR_CLR DMA Channel Source Address Decrement Enable Clear 0x814 32 read-write n 0x0 0xFFFFFFFF CHAN Disable Source Address Decrement 0 27 write-only SRCADDR_SET DMA Channel Source Address Decrement Enable Set 0x810 32 read-write n 0x0 0xFFFFFFFF CHAN Source Address Decrement Status 0 27 read-write STAT DMA Status 0x0 32 read-write n 0x1A0000 0xFFFFFFFF CHANM1 Number of Available DMA Channels Minus 1 16 5 read-only MEN Enable Status of the Controller 0 1 read-only SWREQ DMA Channel Software Request 0x14 32 read-write n 0x0 0xFFFFFFFF CHAN Generate Software Request 0 27 write-only FLCC0 Flash Controller FLCC0 0x40018000 0x0 0x100 registers n ABORT_EN_HI IRQ Abort Enable (Upper Bits) 0x40 32 read-write n 0x0 0xFFFFFFFF VALUE VALUE[63:32] Sys IRQ Abort Enable 0 32 read-write ABORT_EN_LO IRQ Abort Enable (Lower Bits) 0x3C 32 read-write n 0x0 0xFFFFFFFF VALUE VALUE[31:0] Sys IRQ Abort Enable 0 32 read-write CMD Command 0x8 32 read-write n 0x0 0xFFFFFFFF VALUE Commands 0 4 read-write IDLE IDLE 0 ABORT ABORT 1 SLEEP Requests flash to enter Sleep mode 2 SIGN SIGN 3 WRITE WRITE 4 BLANK_CHECK Checks all of User Space fails if any bits in user space are cleared 5 ERASEPAGE ERASEPAGE 6 MASSERASE MASSERASE 7 ECC_ADDR ECC Status (Address) 0x48 32 read-write n 0x0 0xFFFFFFFF VALUE This register has the address for which ECC error is detected 0 20 read-only ECC_CFG ECC Configuration 0x44 32 read-write n 0x2 0xFFFFFFFF EN ECC Enable 0 1 read-write INFOEN Info space ECC Enable bit 1 1 read-write PTR ECC start page pointer 8 24 read-write IEN Interrupt Enable 0x4 32 read-write n 0x60 0xFFFFFFFF CMDCMPLT Command complete interrupt enable 0 1 read-write CMDFAIL Command fail interrupt enable 2 1 read-write ECC_CORRECT Control whether to generate bus errors, interrupts, or neither in response to 1-bit ECC Correction events 4 2 read-write NONE_cor Do not generate a response to ECC events 0 BUS_ERR_cor Generate Bus Errors in response to ECC events 1 IRQ_cor Generate IRQs in response to ECC events 2 ECC_ERROR Control whether to generate bus errors, interrupts, or neither in response to 2-bit ECC Error events 6 2 read-write NONE_err Do not generate a response to ECC events 0 BUS_ERR_err Generate Bus Errors in response to ECC events 1 IRQ_err Generate IRQs in response to ECC events 2 WRALCMPLT Write almost complete interrupt enable 1 1 read-write KEY Key 0x20 32 read-write n 0x0 0xFFFFFFFF VALUE Key register 0 32 write-only KH_ADDR Write Address 0xC 32 read-write n 0x0 0xFFFFFFFF VALUE Address to be written on a WRITE command 3 17 read-write KH_DATA0 Write Lower Data 0x10 32 read-write n 0xFFFFFFFF 0xFFFFFFFF VALUE Lower half of 64-bit dual word data to be written on a Write command 0 32 read-write KH_DATA1 Write Upper Data 0x14 32 read-write n 0xFFFFFFFF 0xFFFFFFFF VALUE Upper half of 64-bit dual word data to be written on a Write command 0 32 read-write PAGE_ADDR0 Lower Page Address 0x18 32 read-write n 0x0 0xFFFFFFFF VALUE Lower address bits of the page address 10 10 read-write PAGE_ADDR1 Upper Page Address 0x1C 32 read-write n 0x0 0xFFFFFFFF VALUE Upper address bits of the page address 10 10 read-write POR_SEC Flash Security 0x50 32 read-write n 0x0 0xFFFFFFFF SECURE Set this bit to prevent read or write access to User Space (sticky when set) 0 1 read-write SIGNATURE Signature 0x2C 32 read-write n 0x0 0xFFFFFFFF VALUE Read signature 0 32 read-only STAT Status 0x0 32 read-write n 0x0 0xFFFFFFFF ACCESS_MODE Access Mode 31 1 read-only Direct Flash controller is currently in Direct Access mode user access to all registers is enabled 0 Indirect Flash Controller is currently in Indirect Access mode user access to registers is limited to read-only access of the status register. Full register access will be restored when the Cryptographic module releases control of the flash controller (crypto completes the ongoing operation within the protected key storage region) 1 CACHESRAMPERR SRAM parity errors in Cache Controller 29 1 read-only CMDBUSY Command busy 0 1 read-only CMDCOMP Command complete 2 1 read-only CMDFAIL Provides information on command failures 4 2 read-only ECCDCODE DCode AHB Bus Error ECC status 27 2 read-only ECCERRCMD ECC errors detected during user issued SIGN command 7 2 read-only ECCERRCNT ECC correction counter 17 3 read-only ECCICODE ICode AHB Bus Error ECC status 25 2 read-only ECCINFOSIGN ECC status of flash initialization 15 2 read-only ECCRDERR ECC IRQ cause 9 2 read-only INIT Flash controller initialization in progress 14 1 read-only OVERLAP Overlapping Command 11 1 read-write SIGNERR Signature check failure during initialization 13 1 read-only SLEEPING Flash array is in low power (sleep) mode 6 1 read-only WRALCOMP Write almost complete 3 1 read-only WRCLOSE WRITE registers are closed 1 1 read-only TIME_PARAM0 Time Parameter 0 0x34 32 read-write n 0xB8954950 0xFFFFFFFF DIVREFCLK Divide Reference Clock (by 2) 0 1 read-write TERASE Erase Time 24 4 read-write TNVH NVSTR Hold time 16 4 read-write TNVH1 NVSTR Hold time during Mass Erase 28 4 read-write TNVS PROG/ERASE to NVSTR setup time 4 4 read-write TPGS NVSTR to Program setup time 8 4 read-write TPROG Program time 12 4 read-write TRCV Recovery time 20 4 read-write TIME_PARAM1 Time Parameter 1 0x38 32 read-write n 0x4 0xFFFFFFFF CURWAITSTATES Current wait states [2:0] 8 3 read-only TWK Wake up time 0 4 read-write WAITSTATES Number of wait states to access flash 4 3 read-write UCFG User Configuration 0x30 32 read-write n 0x0 0xFFFFFFFF AUTOINCEN Auto Address Increment for Key Hole Access 1 1 read-write KHDMAEN Key hole DMA enable 0 1 read-write VOL_CFG Volatile Flash Configuration 0x54 32 read-write n 0x1 0xFFFFFFFF INFO_REMAP Alias the info space to the base address of user space 0 1 read-write WRPROT Write Protection 0x28 32 read-write n 0xFFFFFFFF 0xFFFFFFFF WORD Clear bits to write protect related groups of user space pages 0 32 read-write WR_ABORT_ADDR Write Abort Address 0x24 32 read-write n 0x0 0xFFFFFFFF VALUE Address of recently aborted write command 0 32 read-only FLCC0_CACHE Cache Controller FLCC0_CACHE 0x40018058 0x0 0x100 registers n KEY Cache Key Register 0x8 32 read-write n 0x0 0xFFFFFFFF VALUE Cache Key 0 32 write-only SETUP Cache Setup Register 0x4 32 read-write n 0x0 0xFFFFFFFF ICEN If this bit set, I-Cache is enabled for AHB accesses 0 1 read-write LCKIC If this bit is set, I-Cache contents are locked 1 1 read-write STAT Cache Status Register 0x0 32 read-write n 0x0 0xFFFFFFFF ICEN If this bit is set, I-Cache is enabled 0 1 read-only GPIO0 General-Purpose Input/Output GPIO0 0x40020000 0x0 0x50 registers n CFG Port Configuration 0x0 32 read-write n 0x0 0xFFFFFFFF PIN00 Pin 0 configuration bits 0 2 read-write PIN01 Pin 1 configuration bits 2 2 read-write PIN02 Pin 2 configuration bits 4 2 read-write PIN03 Pin 3 configuration bits 6 2 read-write PIN04 Pin 4 configuration bits 8 2 read-write PIN05 Pin 5 configuration bits 10 2 read-write PIN06 Pin 6 configuration bits 12 2 read-write PIN07 Pin 7 configuration bits 14 2 read-write PIN08 Pin 8 configuration bits 16 2 read-write PIN09 Pin 9 configuration bits 18 2 read-write PIN10 Pin 10 configuration bits 20 2 read-write PIN11 Pin 11 configuration bits 22 2 read-write PIN12 Pin 12 configuration bits 24 2 read-write PIN13 Pin 13 configuration bits 26 2 read-write PIN14 Pin 14 configuration bits 28 2 read-write PIN15 Pin 15 configuration bits 30 2 read-write CLR Port Data Out Clear 0x1C 16 read-write n 0x0 0xFFFFFFFF VALUE Set the output low for the port pin 0 16 write-only DS Port Drive Strength Select 0x34 16 read-write n 0x0 0xFFFFFFFF PIN00 Drive Strength Pin 00 0 1 read-write SINGLE_PIN00 Single Drive Strength 0 DOUBLE_PIN00 Double Drive Strength 1 PIN01 Drive Strength Pin 01 1 1 read-write SINGLE_PIN01 Single Drive Strength 0 DOUBLE_PIN01 Double Drive Strength 1 PIN02 Drive Strength Pin 02 2 1 read-write SINGLE_PIN02 Single Drive Strength 0 DOUBLE_PIN02 Double Drive Strength 1 PIN03 Drive Strength Pin 03 3 1 read-write SINGLE_PIN03 Single Drive Strength 0 DOUBLE_PIN03 Double Drive Strength 1 PIN04 Drive Strength Pin 04 4 1 read-write SINGLE_PIN04 Single Drive Strength 0 DOUBLE_PIN04 Double Drive Strength 1 PIN05 Drive Strength Pin 05 5 1 read-write SINGLE_PIN05 Single Drive Strength 0 DOUBLE_PIN05 Double Drive Strength 1 PIN06 Drive Strength Pin 06 6 1 read-write SINGLE_PIN06 Single Drive Strength 0 DOUBLE_PIN06 Double Drive Strength 1 PIN07 Drive Strength Pin 07 7 1 read-write SINGLE_PIN07 Single Drive Strength 0 DOUBLE_PIN07 Double Drive Strength 1 PIN08 Drive Strength Pin 08 8 1 read-write SINGLE_PIN08 Single Drive Strength 0 DOUBLE_PIN08 Double Drive Strength 1 PIN09 Drive Strength Pin 09 9 1 read-write SINGLE_PIN09 Single Drive Strength 0 DOUBLE_PIN09 Double Drive Strength 1 PIN10 Drive Strength Pin 10 10 1 read-write SINGLE_PIN10 Single Drive Strength 0 DOUBLE_PIN10 Double Drive Strength 1 PIN11 Drive Strength Pin 11 11 1 read-write SINGLE_PIN11 Single Drive Strength 0 DOUBLE_PIN11 Double Drive Strength 1 PIN12 Drive Strength Pin 12 12 1 read-write SINGLE_PIN12 Single Drive Strength 0 DOUBLE_PIN12 Double Drive Strength 1 PIN13 Drive Strength Pin 13 13 1 read-write SINGLE_PIN13 Single Drive Strength 0 DOUBLE_PIN13 Double Drive Strength 1 PIN14 Drive Strength Pin 14 14 1 read-write SINGLE_PIN14 Single Drive Strength 0 DOUBLE_PIN14 Double Drive Strength 1 PIN15 Drive Strength Pin 15 15 1 read-write SINGLE_PIN15 Single Drive Strength 0 DOUBLE_PIN15 Double Drive Strength 1 IEN Port Input Path Enable 0xC 16 read-write n 0x0 0xFFFFFFFF VALUE Input path enable 0 16 read-write IENA Port Interrupt A Enable 0x28 16 read-write n 0x0 0xFFFFFFFF VALUE Interrupt A enable 0 16 read-write IENB Port Interrupt B Enable 0x2C 16 read-write n 0x0 0xFFFFFFFF VALUE Interrupt B enable 0 16 read-write IN Port Registered Data Input 0x10 16 read-write n 0x0 0xFFFFFFFF VALUE Registered data input 0 16 read-only INT Port Interrupt Status 0x30 16 read-write n 0x0 0xFFFFFFFF VALUE Interrupt Status 0 16 read-write OEN Port Output Enable 0x4 16 read-write n 0x0 0xFFFFFFFF VALUE Pin Output Drive enable 0 16 read-write OUT Port Data Output 0x14 16 read-write n 0x0 0xFFFFFFFF VALUE Data out 0 16 read-write PE Port Output Pull-up/Pull-down Enable 0x8 16 read-write n 0xC0 0xFFFFFFFF VALUE Pin Pull enable 0 16 read-write POL Port Interrupt Polarity 0x24 16 read-write n 0x0 0xFFFFFFFF VALUE Interrupt polarity 0 16 read-write SET Port Data Out Set 0x18 16 read-write n 0x0 0xFFFFFFFF VALUE Set the output HIGH for the pin 0 16 write-only TGL Port Pin Toggle 0x20 16 read-write n 0x0 0xFFFFFFFF VALUE Toggle the output of the port pin 0 16 write-only GPIO1 General-Purpose Input/Output GPIO0 0x40020040 0x0 0x50 registers n CFG Port Configuration 0x0 32 read-write n 0x0 0xFFFFFFFF PIN00 Pin 0 configuration bits 0 2 read-write PIN01 Pin 1 configuration bits 2 2 read-write PIN02 Pin 2 configuration bits 4 2 read-write PIN03 Pin 3 configuration bits 6 2 read-write PIN04 Pin 4 configuration bits 8 2 read-write PIN05 Pin 5 configuration bits 10 2 read-write PIN06 Pin 6 configuration bits 12 2 read-write PIN07 Pin 7 configuration bits 14 2 read-write PIN08 Pin 8 configuration bits 16 2 read-write PIN09 Pin 9 configuration bits 18 2 read-write PIN10 Pin 10 configuration bits 20 2 read-write PIN11 Pin 11 configuration bits 22 2 read-write PIN12 Pin 12 configuration bits 24 2 read-write PIN13 Pin 13 configuration bits 26 2 read-write PIN14 Pin 14 configuration bits 28 2 read-write PIN15 Pin 15 configuration bits 30 2 read-write CLR Port Data Out Clear 0x1C 16 read-write n 0x0 0xFFFFFFFF VALUE Set the output low for the port pin 0 16 write-only DS Port Drive Strength Select 0x34 16 read-write n 0x0 0xFFFFFFFF PIN00 Drive Strength Pin 00 0 1 read-write SINGLE_PIN00 Single Drive Strength 0 DOUBLE_PIN00 Double Drive Strength 1 PIN01 Drive Strength Pin 01 1 1 read-write SINGLE_PIN01 Single Drive Strength 0 DOUBLE_PIN01 Double Drive Strength 1 PIN02 Drive Strength Pin 02 2 1 read-write SINGLE_PIN02 Single Drive Strength 0 DOUBLE_PIN02 Double Drive Strength 1 PIN03 Drive Strength Pin 03 3 1 read-write SINGLE_PIN03 Single Drive Strength 0 DOUBLE_PIN03 Double Drive Strength 1 PIN04 Drive Strength Pin 04 4 1 read-write SINGLE_PIN04 Single Drive Strength 0 DOUBLE_PIN04 Double Drive Strength 1 PIN05 Drive Strength Pin 05 5 1 read-write SINGLE_PIN05 Single Drive Strength 0 DOUBLE_PIN05 Double Drive Strength 1 PIN06 Drive Strength Pin 06 6 1 read-write SINGLE_PIN06 Single Drive Strength 0 DOUBLE_PIN06 Double Drive Strength 1 PIN07 Drive Strength Pin 07 7 1 read-write SINGLE_PIN07 Single Drive Strength 0 DOUBLE_PIN07 Double Drive Strength 1 PIN08 Drive Strength Pin 08 8 1 read-write SINGLE_PIN08 Single Drive Strength 0 DOUBLE_PIN08 Double Drive Strength 1 PIN09 Drive Strength Pin 09 9 1 read-write SINGLE_PIN09 Single Drive Strength 0 DOUBLE_PIN09 Double Drive Strength 1 PIN10 Drive Strength Pin 10 10 1 read-write SINGLE_PIN10 Single Drive Strength 0 DOUBLE_PIN10 Double Drive Strength 1 PIN11 Drive Strength Pin 11 11 1 read-write SINGLE_PIN11 Single Drive Strength 0 DOUBLE_PIN11 Double Drive Strength 1 PIN12 Drive Strength Pin 12 12 1 read-write SINGLE_PIN12 Single Drive Strength 0 DOUBLE_PIN12 Double Drive Strength 1 PIN13 Drive Strength Pin 13 13 1 read-write SINGLE_PIN13 Single Drive Strength 0 DOUBLE_PIN13 Double Drive Strength 1 PIN14 Drive Strength Pin 14 14 1 read-write SINGLE_PIN14 Single Drive Strength 0 DOUBLE_PIN14 Double Drive Strength 1 PIN15 Drive Strength Pin 15 15 1 read-write SINGLE_PIN15 Single Drive Strength 0 DOUBLE_PIN15 Double Drive Strength 1 IEN Port Input Path Enable 0xC 16 read-write n 0x0 0xFFFFFFFF VALUE Input path enable 0 16 read-write IENA Port Interrupt A Enable 0x28 16 read-write n 0x0 0xFFFFFFFF VALUE Interrupt A enable 0 16 read-write IENB Port Interrupt B Enable 0x2C 16 read-write n 0x0 0xFFFFFFFF VALUE Interrupt B enable 0 16 read-write IN Port Registered Data Input 0x10 16 read-write n 0x0 0xFFFFFFFF VALUE Registered data input 0 16 read-only INT Port Interrupt Status 0x30 16 read-write n 0x0 0xFFFFFFFF VALUE Interrupt Status 0 16 read-write OEN Port Output Enable 0x4 16 read-write n 0x0 0xFFFFFFFF VALUE Pin Output Drive enable 0 16 read-write OUT Port Data Output 0x14 16 read-write n 0x0 0xFFFFFFFF VALUE Data out 0 16 read-write PE Port Output Pull-up/Pull-down Enable 0x8 16 read-write n 0xC0 0xFFFFFFFF VALUE Pin Pull enable 0 16 read-write POL Port Interrupt Polarity 0x24 16 read-write n 0x0 0xFFFFFFFF VALUE Interrupt polarity 0 16 read-write SET Port Data Out Set 0x18 16 read-write n 0x0 0xFFFFFFFF VALUE Set the output HIGH for the pin 0 16 write-only TGL Port Pin Toggle 0x20 16 read-write n 0x0 0xFFFFFFFF VALUE Toggle the output of the port pin 0 16 write-only GPIO2 General-Purpose Input/Output GPIO0 0x40020080 0x0 0x50 registers n CFG Port Configuration 0x0 32 read-write n 0x0 0xFFFFFFFF PIN00 Pin 0 configuration bits 0 2 read-write PIN01 Pin 1 configuration bits 2 2 read-write PIN02 Pin 2 configuration bits 4 2 read-write PIN03 Pin 3 configuration bits 6 2 read-write PIN04 Pin 4 configuration bits 8 2 read-write PIN05 Pin 5 configuration bits 10 2 read-write PIN06 Pin 6 configuration bits 12 2 read-write PIN07 Pin 7 configuration bits 14 2 read-write PIN08 Pin 8 configuration bits 16 2 read-write PIN09 Pin 9 configuration bits 18 2 read-write PIN10 Pin 10 configuration bits 20 2 read-write PIN11 Pin 11 configuration bits 22 2 read-write PIN12 Pin 12 configuration bits 24 2 read-write PIN13 Pin 13 configuration bits 26 2 read-write PIN14 Pin 14 configuration bits 28 2 read-write PIN15 Pin 15 configuration bits 30 2 read-write CLR Port Data Out Clear 0x1C 16 read-write n 0x0 0xFFFFFFFF VALUE Set the output low for the port pin 0 16 write-only DS Port Drive Strength Select 0x34 16 read-write n 0x0 0xFFFFFFFF PIN00 Drive Strength Pin 00 0 1 read-write SINGLE_PIN00 Single Drive Strength 0 DOUBLE_PIN00 Double Drive Strength 1 PIN01 Drive Strength Pin 01 1 1 read-write SINGLE_PIN01 Single Drive Strength 0 DOUBLE_PIN01 Double Drive Strength 1 PIN02 Drive Strength Pin 02 2 1 read-write SINGLE_PIN02 Single Drive Strength 0 DOUBLE_PIN02 Double Drive Strength 1 PIN03 Drive Strength Pin 03 3 1 read-write SINGLE_PIN03 Single Drive Strength 0 DOUBLE_PIN03 Double Drive Strength 1 PIN04 Drive Strength Pin 04 4 1 read-write SINGLE_PIN04 Single Drive Strength 0 DOUBLE_PIN04 Double Drive Strength 1 PIN05 Drive Strength Pin 05 5 1 read-write SINGLE_PIN05 Single Drive Strength 0 DOUBLE_PIN05 Double Drive Strength 1 PIN06 Drive Strength Pin 06 6 1 read-write SINGLE_PIN06 Single Drive Strength 0 DOUBLE_PIN06 Double Drive Strength 1 PIN07 Drive Strength Pin 07 7 1 read-write SINGLE_PIN07 Single Drive Strength 0 DOUBLE_PIN07 Double Drive Strength 1 PIN08 Drive Strength Pin 08 8 1 read-write SINGLE_PIN08 Single Drive Strength 0 DOUBLE_PIN08 Double Drive Strength 1 PIN09 Drive Strength Pin 09 9 1 read-write SINGLE_PIN09 Single Drive Strength 0 DOUBLE_PIN09 Double Drive Strength 1 PIN10 Drive Strength Pin 10 10 1 read-write SINGLE_PIN10 Single Drive Strength 0 DOUBLE_PIN10 Double Drive Strength 1 PIN11 Drive Strength Pin 11 11 1 read-write SINGLE_PIN11 Single Drive Strength 0 DOUBLE_PIN11 Double Drive Strength 1 PIN12 Drive Strength Pin 12 12 1 read-write SINGLE_PIN12 Single Drive Strength 0 DOUBLE_PIN12 Double Drive Strength 1 PIN13 Drive Strength Pin 13 13 1 read-write SINGLE_PIN13 Single Drive Strength 0 DOUBLE_PIN13 Double Drive Strength 1 PIN14 Drive Strength Pin 14 14 1 read-write SINGLE_PIN14 Single Drive Strength 0 DOUBLE_PIN14 Double Drive Strength 1 PIN15 Drive Strength Pin 15 15 1 read-write SINGLE_PIN15 Single Drive Strength 0 DOUBLE_PIN15 Double Drive Strength 1 IEN Port Input Path Enable 0xC 16 read-write n 0x0 0xFFFFFFFF VALUE Input path enable 0 16 read-write IENA Port Interrupt A Enable 0x28 16 read-write n 0x0 0xFFFFFFFF VALUE Interrupt A enable 0 16 read-write IENB Port Interrupt B Enable 0x2C 16 read-write n 0x0 0xFFFFFFFF VALUE Interrupt B enable 0 16 read-write IN Port Registered Data Input 0x10 16 read-write n 0x0 0xFFFFFFFF VALUE Registered data input 0 16 read-only INT Port Interrupt Status 0x30 16 read-write n 0x0 0xFFFFFFFF VALUE Interrupt Status 0 16 read-write OEN Port Output Enable 0x4 16 read-write n 0x0 0xFFFFFFFF VALUE Pin Output Drive enable 0 16 read-write OUT Port Data Output 0x14 16 read-write n 0x0 0xFFFFFFFF VALUE Data out 0 16 read-write PE Port Output Pull-up/Pull-down Enable 0x8 16 read-write n 0xC0 0xFFFFFFFF VALUE Pin Pull enable 0 16 read-write POL Port Interrupt Polarity 0x24 16 read-write n 0x0 0xFFFFFFFF VALUE Interrupt polarity 0 16 read-write SET Port Data Out Set 0x18 16 read-write n 0x0 0xFFFFFFFF VALUE Set the output HIGH for the pin 0 16 write-only TGL Port Pin Toggle 0x20 16 read-write n 0x0 0xFFFFFFFF VALUE Toggle the output of the port pin 0 16 write-only GPIO3 General-Purpose Input/Output GPIO0 0x400200C0 0x0 0x50 registers n CFG Port Configuration 0x0 32 read-write n 0x0 0xFFFFFFFF PIN00 Pin 0 configuration bits 0 2 read-write PIN01 Pin 1 configuration bits 2 2 read-write PIN02 Pin 2 configuration bits 4 2 read-write PIN03 Pin 3 configuration bits 6 2 read-write PIN04 Pin 4 configuration bits 8 2 read-write PIN05 Pin 5 configuration bits 10 2 read-write PIN06 Pin 6 configuration bits 12 2 read-write PIN07 Pin 7 configuration bits 14 2 read-write PIN08 Pin 8 configuration bits 16 2 read-write PIN09 Pin 9 configuration bits 18 2 read-write PIN10 Pin 10 configuration bits 20 2 read-write PIN11 Pin 11 configuration bits 22 2 read-write PIN12 Pin 12 configuration bits 24 2 read-write PIN13 Pin 13 configuration bits 26 2 read-write PIN14 Pin 14 configuration bits 28 2 read-write PIN15 Pin 15 configuration bits 30 2 read-write CLR Port Data Out Clear 0x1C 16 read-write n 0x0 0xFFFFFFFF VALUE Set the output low for the port pin 0 16 write-only DS Port Drive Strength Select 0x34 16 read-write n 0x0 0xFFFFFFFF PIN00 Drive Strength Pin 00 0 1 read-write SINGLE_PIN00 Single Drive Strength 0 DOUBLE_PIN00 Double Drive Strength 1 PIN01 Drive Strength Pin 01 1 1 read-write SINGLE_PIN01 Single Drive Strength 0 DOUBLE_PIN01 Double Drive Strength 1 PIN02 Drive Strength Pin 02 2 1 read-write SINGLE_PIN02 Single Drive Strength 0 DOUBLE_PIN02 Double Drive Strength 1 PIN03 Drive Strength Pin 03 3 1 read-write SINGLE_PIN03 Single Drive Strength 0 DOUBLE_PIN03 Double Drive Strength 1 PIN04 Drive Strength Pin 04 4 1 read-write SINGLE_PIN04 Single Drive Strength 0 DOUBLE_PIN04 Double Drive Strength 1 PIN05 Drive Strength Pin 05 5 1 read-write SINGLE_PIN05 Single Drive Strength 0 DOUBLE_PIN05 Double Drive Strength 1 PIN06 Drive Strength Pin 06 6 1 read-write SINGLE_PIN06 Single Drive Strength 0 DOUBLE_PIN06 Double Drive Strength 1 PIN07 Drive Strength Pin 07 7 1 read-write SINGLE_PIN07 Single Drive Strength 0 DOUBLE_PIN07 Double Drive Strength 1 PIN08 Drive Strength Pin 08 8 1 read-write SINGLE_PIN08 Single Drive Strength 0 DOUBLE_PIN08 Double Drive Strength 1 PIN09 Drive Strength Pin 09 9 1 read-write SINGLE_PIN09 Single Drive Strength 0 DOUBLE_PIN09 Double Drive Strength 1 PIN10 Drive Strength Pin 10 10 1 read-write SINGLE_PIN10 Single Drive Strength 0 DOUBLE_PIN10 Double Drive Strength 1 PIN11 Drive Strength Pin 11 11 1 read-write SINGLE_PIN11 Single Drive Strength 0 DOUBLE_PIN11 Double Drive Strength 1 PIN12 Drive Strength Pin 12 12 1 read-write SINGLE_PIN12 Single Drive Strength 0 DOUBLE_PIN12 Double Drive Strength 1 PIN13 Drive Strength Pin 13 13 1 read-write SINGLE_PIN13 Single Drive Strength 0 DOUBLE_PIN13 Double Drive Strength 1 PIN14 Drive Strength Pin 14 14 1 read-write SINGLE_PIN14 Single Drive Strength 0 DOUBLE_PIN14 Double Drive Strength 1 PIN15 Drive Strength Pin 15 15 1 read-write SINGLE_PIN15 Single Drive Strength 0 DOUBLE_PIN15 Double Drive Strength 1 IEN Port Input Path Enable 0xC 16 read-write n 0x0 0xFFFFFFFF VALUE Input path enable 0 16 read-write IENA Port Interrupt A Enable 0x28 16 read-write n 0x0 0xFFFFFFFF VALUE Interrupt A enable 0 16 read-write IENB Port Interrupt B Enable 0x2C 16 read-write n 0x0 0xFFFFFFFF VALUE Interrupt B enable 0 16 read-write IN Port Registered Data Input 0x10 16 read-write n 0x0 0xFFFFFFFF VALUE Registered data input 0 16 read-only INT Port Interrupt Status 0x30 16 read-write n 0x0 0xFFFFFFFF VALUE Interrupt Status 0 16 read-write OEN Port Output Enable 0x4 16 read-write n 0x0 0xFFFFFFFF VALUE Pin Output Drive enable 0 16 read-write OUT Port Data Output 0x14 16 read-write n 0x0 0xFFFFFFFF VALUE Data out 0 16 read-write PE Port Output Pull-up/Pull-down Enable 0x8 16 read-write n 0xC0 0xFFFFFFFF VALUE Pin Pull enable 0 16 read-write POL Port Interrupt Polarity 0x24 16 read-write n 0x0 0xFFFFFFFF VALUE Interrupt polarity 0 16 read-write SET Port Data Out Set 0x18 16 read-write n 0x0 0xFFFFFFFF VALUE Set the output HIGH for the pin 0 16 write-only TGL Port Pin Toggle 0x20 16 read-write n 0x0 0xFFFFFFFF VALUE Toggle the output of the port pin 0 16 write-only I2C0 I2C Master/Slave I2C0 0x40003000 0x0 0x2C registers n I2C_SLV_EVT Slave Event 17 I2C_MST_EVT Master Event 18 ADDR1 Master Address Byte 1 0x18 16 read-write n 0x0 0xFFFFFFFF VALUE Address Byte 1 0 8 read-write ADDR2 Master Address Byte 2 0x1C 16 read-write n 0x0 0xFFFFFFFF VALUE Address Byte 2 0 8 read-write ALT Hardware General Call ID 0x38 16 read-write n 0x0 0xFFFFFFFF ID Slave Alt 0 8 read-write ASTRETCH_SCL Automatic Stretch SCL 0x58 16 read-write n 0x0 0xFFFFFFFF MST Master Automatic Stretch Mode 0 4 read-write MSTTMO Master Automatic Stretch Timeout 8 1 read-only SLV Slave Automatic Stretch Mode 4 4 read-write SLVTMO Slave Automatic Stretch Timeout 9 1 read-only BYT Start Byte 0x20 16 read-write n 0x0 0xFFFFFFFF SBYTE Start Byte 0 8 read-write DIV Serial Clock Period Divisor 0x24 16 read-write n 0x1F1F 0xFFFFFFFF HIGH Serial Clock High Time 8 8 read-write LOW Serial Clock Low Time 0 8 read-write ID0 First Slave Address Device ID 0x3C 16 read-write n 0x0 0xFFFFFFFF VALUE Slave Device ID 0 0 8 read-write ID1 Second Slave Address Device ID 0x40 16 read-write n 0x0 0xFFFFFFFF VALUE Slave Device ID 1 0 8 read-write ID2 Third Slave Address Device ID 0x44 16 read-write n 0x0 0xFFFFFFFF VALUE Slave Device ID 2 0 8 read-write ID3 Fourth Slave Address Device ID 0x48 16 read-write n 0x0 0xFFFFFFFF VALUE Slave Device ID 3 0 8 read-write MCRXCNT Master Current Receive Data Count 0x14 16 read-write n 0x0 0xFFFFFFFF VALUE Current Receive Count 0 8 read-only MCTL Master Control 0x0 16 read-write n 0x0 0xFFFFFFFF BUSCLR Bus-Clear Enable 12 1 read-write COMPLETE Start Back-off Disable 1 1 read-write IENACK ACK Not Received Interrupt Enable 7 1 read-write IENALOST Arbitration Lost Interrupt Enable 6 1 read-write IENCMP Transaction Completed (or Stop Detected) Interrupt Enable 8 1 read-write IENMRX Receive Request Interrupt Enable 4 1 read-write IENMTX Transmit Request Interrupt Enable 5 1 read-write LOOPBACK Internal Loopback Enable 2 1 read-write MASEN Master Enable 0 1 read-write MRXDMA Enable Master Rx DMA Request 10 1 write-only MTXDMA Enable Master Tx DMA Request 11 1 write-only MXMITDEC Decrement Master Tx FIFO Status When a Byte Txed 9 1 read-write STOPBUSCLR Prestop Bus Clear 13 1 read-write STRETCHSCL Stretch SCL Enable 3 1 read-write MRX Master Receive Data 0x8 16 read-write n 0x0 0xFFFFFFFF VALUE Master Receive Register 0 8 read-only MRXCNT Master Receive Data Count 0x10 16 read-write n 0x0 0xFFFFFFFF EXTEND Extended Read 8 1 read-write VALUE Receive Count 0 8 read-write MSTAT Master Status 0x4 16 read-write n 0x6000 0xFFFFFFFF ALOST Arbitration Lost 5 1 read-only LINEBUSY Line is Busy 10 1 read-only MBUSY Master Busy 6 1 read-only MRXOVR Master Receive FIFO Overflow 9 1 read-only MRXREQ Master Receive Request 3 1 read-only MSTOP STOP Driven by This I2C Master 11 1 read-only MTXF Master Transmit FIFO Status 0 2 read-only FIFO_EMPTY FIFO Empty. 0 FIFO_1BYTE 1 byte in FIFO. 2 FIFO_FULL FIFO Full. 3 MTXREQ Master Transmit Request/Clear Master Transmit Interrupt 2 1 read-write MTXUNDR Master Transmit Underflow 12 1 read-only NACKADDR ACK Not Received in Response to an Address 4 1 read-only NACKDATA ACK Not Received in Response to Data Write 7 1 read-only SCLFILT State of SCL Line 14 1 read-only SDAFILT State of SDA Line 13 1 read-only TCOMP Transaction Complete or Stop Detected 8 1 read-only MTX Master Transmit Data 0xC 16 read-write n 0x0 0xFFFFFFFF VALUE Master Transmit Register 0 8 read-write SCTL Slave Control 0x28 16 read-write n 0x0 0xFFFFFFFF ADR10EN Enabled 10-bit Addressing 1 1 read-write EARLYTXR Early Transmit Request Mode 5 1 read-write GCEN General Call Enable 2 1 read-write GCSBCLR General Call Status Bit Clear 4 1 write-only HGCEN Hardware General Call Enable 3 1 read-write IENREPST Repeated Start Interrupt Enable 12 1 read-write IENSRX Slave Receive Request Interrupt Enable 9 1 read-write IENSTOP Stop Condition Detected Interrupt Enable 8 1 read-write IENSTX Slave Transmit Request Interrupt Enable 10 1 read-write NACK NACK Next Communication 7 1 read-write SLVEN Slave Enable 0 1 read-write SRXDMA Enable Slave Rx DMA Request 13 1 read-write STXDEC Decrement Slave Tx FIFO Status When a Byte is Txed 11 1 read-write STXDMA Enable Slave Tx DMA Request 14 1 read-write SHCTL Shared Control 0x50 16 read-write n 0x0 0xFFFFFFFF RST Reset START STOP Detect Circuit 0 1 write-only SRX Slave Receive 0x30 16 read-write n 0x0 0xFFFFFFFF VALUE Slave Receive Register 0 8 read-only SSTAT Slave I2C Status/Error/IRQ 0x2C 16 read-write n 0x1 0xFFFFFFFF GCID General ID 8 2 read-only GCINT General Call Interrupt 7 1 read-only IDMAT Device ID Matched 11 2 read-only NOACK ACK Not Generated by the Slave 5 1 read-only REPSTART Repeated Start and Matching Address 13 1 read-only SBUSY Slave Busy 6 1 read-only SRXOVR Slave Receive FIFO Overflow 4 1 read-only SRXREQ Slave Receive Request 3 1 read-only START Start and Matching Address 14 1 read-only STOP Stop After Start and Matching Address 10 1 read-only STXFSEREQ Slave Tx FIFO Status or Early Request 0 1 read-write STXREQ Slave Transmit Request/Slave Transmit Interrupt 2 1 read-only STXUNDR Slave Transmit FIFO Underflow 1 1 read-only STAT Master and Slave FIFO Status 0x4C 16 read-write n 0x0 0xFFFFFFFF MFLUSH Flush the Master Transmit FIFO 9 1 write-only MRXF Master Receive FIFO Status 6 2 read-only MTXF Master Transmit FIFO Status 4 2 read-only SFLUSH Flush the Slave Transmit FIFO 8 1 write-only SRXF Slave Receive FIFO Status 2 2 read-only STXF Slave Transmit FIFO Status 0 2 read-only STX Slave Transmit 0x34 16 read-write n 0x0 0xFFFFFFFF VALUE Slave Transmit Register 0 8 read-write TCTL Timing Control Register 0x54 16 read-write n 0x5 0xFFFFFFFF FILTEROFF Input Filter Control 8 1 read-write THDATIN Data in Hold Start 0 5 read-write NVIC0 Cortex Interrupt Controller NVIC0 0xE000E000 0x0 0x1000 registers n INTACT0 IRQ0..31 Active Bit 0x300 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ0..31 Active Bit 0 32 read-write INTACT1 IRQ32..63 Active Bit 0x304 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ32..63 Active Bit 0 32 read-write INTACT2 IRQ64..95 Active Bit 0x308 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ64..95 Active Bit 0 32 read-write INTAFR0 Auxiliary Feature Register 0 0xD4C 32 read-write n 0x0 0xFFFFFFFF VALUE Auxiliary Feature Register 0 0 32 read-write INTAFSR Auxiliary Fault Status 0xD3C 32 read-write n 0x0 0xFFFFFFFF VALUE Auxiliary Fault Status 0 32 read-write INTAIRC Application Interrupt/Reset Control 0xD0C 32 read-write n 0x0 0xFFFFFFFF VALUE Application Interrupt/Reset Control 0 32 read-write INTBFAR Bus Fault Address 0xD38 32 read-write n 0x0 0xFFFFFFFF VALUE Bus Fault Address 0 32 read-write INTCFSR Configurable Fault Status 0xD28 32 read-write n 0x0 0xFFFFFFFF VALUE Configurable Fault Status 0 32 read-write INTCID0 Component Identification Bits7:0 0xFF0 32 read-write n 0x0 0xFFFFFFFF VALUE Component Identification Bits7:0 0 32 read-write INTCID1 Component Identification Bits15:8 0xFF4 32 read-write n 0x0 0xFFFFFFFF VALUE Component Identification Bits15:8 0 32 read-write INTCID2 Component Identification Bits16:23 0xFF8 32 read-write n 0x0 0xFFFFFFFF VALUE Component Identification Bits16:23 0 32 read-write INTCID3 Component Identification Bits24:31 0xFFC 32 read-write n 0x0 0xFFFFFFFF VALUE Component Identification Bits24:31 0 32 read-write INTCLRE0 IRQ0..31 Clear_Enable 0x180 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ0..31 Clear_Enable 0 32 read-write INTCLRE1 IRQ32..63 Clear_Enable 0x184 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ32..63 Clear_Enable 0 32 read-write INTCLRE2 IRQ64..95 Clear_Enable 0x188 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ64..95 Clear_Enable 0 32 read-write INTCLRP0 IRQ0..31 Clear_Pending 0x280 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ0..31 Clear_Pending 0 32 read-write INTCLRP1 IRQ32..63 Clear_Pending 0x284 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ32..63 Clear_Pending 0 32 read-write INTCLRP2 IRQ64..95 Clear_Pending 0x288 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ64..95 Clear_Pending 0 32 read-write INTCON0 System Control 0xD10 16 read-write n 0x0 0xFFFFFFFF SLEEPDEEP Deep Sleep Flag for Hibernate Mode 2 1 read-write NO_SLEEPDEEP Sleep Deep is not enabled 0 SLEEPDEEP Sleep Deep is enabled 1 SLEEPONEXIT Sleeps the Core on Exit from an ISR 1 1 read-write NO_SLEEPONEXIT Sleep On Exit is not enabled 0 SLEEPONEXIT Sleep On Exit is enabled 1 INTCON1 Configuration Control 0xD14 32 read-write n 0x0 0xFFFFFFFF VALUE Configuration Control 0 32 read-write INTCPID CPUID Base 0xD00 32 read-write n 0x0 0xFFFFFFFF VALUE CPUID Base 0 32 read-write INTDFR0 Debug Feature Register 0 0xD48 32 read-write n 0x0 0xFFFFFFFF VALUE Debug Feature Register 0 0 32 read-write INTDFSR Debug Fault Status 0xD30 32 read-write n 0x0 0xFFFFFFFF VALUE Debug Fault Status 0 32 read-write INTHFSR Hard Fault Status 0xD2C 32 read-write n 0x0 0xFFFFFFFF VALUE Hard Fault Status 0 32 read-write INTISAR0 ISA Feature Register 0 0xD60 32 read-write n 0x0 0xFFFFFFFF VALUE ISA Feature Register 0 0 32 read-write INTISAR1 ISA Feature Register 1 0xD64 32 read-write n 0x0 0xFFFFFFFF VALUE ISA Feature Register 1 0 32 read-write INTISAR2 ISA Feature Register 2 0xD68 32 read-write n 0x0 0xFFFFFFFF VALUE ISA Feature Register 2 0 32 read-write INTISAR3 ISA Feature Register 3 0xD6C 32 read-write n 0x0 0xFFFFFFFF VALUE ISA Feature Register 3 0 32 read-write INTISAR4 ISA Feature Register 4 0xD70 32 read-write n 0x0 0xFFFFFFFF VALUE ISA Feature Register 4 0 32 read-write INTMMAR Mem Manage Address 0xD34 32 read-write n 0x0 0xFFFFFFFF VALUE Mem Manage Address 0 32 read-write INTMMFR0 Memory Model Feature Register 0 0xD50 32 read-write n 0x0 0xFFFFFFFF VALUE Memory Model Feature Register 0 0 32 read-write INTMMFR1 Memory Model Feature Register 1 0xD54 32 read-write n 0x0 0xFFFFFFFF VALUE Memory Model Feature Register 1 0 32 read-write INTMMFR2 Memory Model Feature Register 2 0xD58 32 read-write n 0x0 0xFFFFFFFF VALUE Memory Model Feature Register 2 0 32 read-write INTMMFR3 Memory Model Feature Register 3 0xD5C 32 read-write n 0x0 0xFFFFFFFF VALUE Memory Model Feature Register 3 0 32 read-write INTNUM Interrupt Control Type 0x4 32 read-write n 0x0 0xFFFFFFFF VALUE Interrupt Control Type 0 32 read-write INTPFR0 Processor Feature Register 0 0xD40 32 read-write n 0x0 0xFFFFFFFF VALUE Processor Feature Register 0 0 32 read-write INTPFR1 Processor Feature Register 1 0xD44 32 read-write n 0x0 0xFFFFFFFF VALUE Processor Feature Register 1 0 32 read-write INTPID0 Peripheral Identification Bits7:0 0xFE0 32 read-write n 0x0 0xFFFFFFFF VALUE Peripheral Identification Bits7:0 0 32 read-write INTPID1 Peripheral Identification Bits15:8 0xFE4 32 read-write n 0x0 0xFFFFFFFF VALUE Peripheral Identification Bits15:8 0 32 read-write INTPID2 Peripheral Identification Bits16:23 0xFE8 32 read-write n 0x0 0xFFFFFFFF VALUE Peripheral Identification Bits16:23 0 32 read-write INTPID3 Peripheral Identification Bits24:31 0xFEC 32 read-write n 0x0 0xFFFFFFFF VALUE Peripheral Identification Bits24:31 0 32 read-write INTPID4 Peripheral Identification Register 4 0xFD0 32 read-write n 0x0 0xFFFFFFFF VALUE Peripheral Identification Register 4 0 32 read-write INTPID5 Peripheral Identification Register 5 0xFD4 32 read-write n 0x0 0xFFFFFFFF VALUE Peripheral Identification Register 5 0 32 read-write INTPID6 Peripheral Identification Register 6 0xFD8 32 read-write n 0x0 0xFFFFFFFF VALUE Peripheral Identification Register 6 0 32 read-write INTPID7 Peripheral Identification Register 7 0xFDC 32 read-write n 0x0 0xFFFFFFFF VALUE Peripheral Identification Register 7 0 32 read-write INTPRI0 IRQ0..3 Priority 0x400 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ0..3 Priority 0 32 read-write INTPRI1 IRQ4..7 Priority 0x404 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ4..7 Priority 0 32 read-write INTPRI10 IRQ40..43 Priority 0x428 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ40..43 Priority 0 32 read-write INTPRI11 IRQ44..47 Priority 0x42C 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ44..47 Priority 0 32 read-write INTPRI12 IRQ48..51 Priority 0x430 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ48..51 Priority 0 32 read-write INTPRI13 IRQ52..55 Priority 0x434 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ52..55 Priority 0 32 read-write INTPRI14 IRQ56..59 Priority 0x438 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ56..59 Priority 0 32 read-write INTPRI15 IRQ60..63 Priority 0x43C 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ60..63 Priority 0 32 read-write INTPRI16 IRQ64..67 Priority 0x440 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ64..67 Priority 0 32 read-write INTPRI17 IRQ68..71 Priority 0x444 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ68..71 Priority 0 32 read-write INTPRI2 IRQ8..11 Priority 0x408 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ8..11 Priority 0 32 read-write INTPRI3 IRQ12..15 Priority 0x40C 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ12..15 Priority 0 32 read-write INTPRI4 IRQ16..19 Priority 0x410 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ16..19 Priority 0 32 read-write INTPRI5 IRQ20..23 Priority 0x414 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ20..23 Priority 0 32 read-write INTPRI6 IRQ24..27 Priority 0x418 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ24..27 Priority 0 32 read-write INTPRI7 IRQ28..31 Priority 0x41C 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ28..31 Priority 0 32 read-write INTPRI8 IRQ32..35 Priority 0x420 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ32..35 Priority 0 32 read-write INTPRI9 IRQ36..39 Priority 0x424 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ36..39 Priority 0 32 read-write INTSETE0 IRQ0..31 Set_Enable 0x100 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ0..31 Set_Enable 0 32 read-write INTSETE1 IRQ32..63 Set_Enable 0x104 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ32..63 Set_Enable 0 32 read-write INTSETE2 IRQ64..95 Set_Enable 0x108 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ64..95 Set_Enable 0 32 read-write INTSETP0 IRQ0..31 Set_Pending 0x200 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ0..31 Set_Pending 0 32 read-write INTSETP1 IRQ32..63 Set_Pending 0x204 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ32..63 Set_Pending 0 32 read-write INTSETP2 IRQ64..95 Set_Pending 0x208 32 read-write n 0x0 0xFFFFFFFF VALUE IRQ64..95 Set_Pending 0 32 read-write INTSHCSR System Handler Control and State 0xD24 32 read-write n 0x0 0xFFFFFFFF VALUE System Handler Control and State 0 32 read-write INTSHPRIO0 System Handlers 4-7 Priority 0xD18 32 read-write n 0x0 0xFFFFFFFF VALUE System Handlers 4-7 Priority 0 32 read-write INTSHPRIO1 System Handlers 8-11 Priority 0xD1C 32 read-write n 0x0 0xFFFFFFFF VALUE System Handlers 8-11 Priority 0 32 read-write INTSHPRIO3 System Handlers 12-15 Priority 0xD20 32 read-write n 0x0 0xFFFFFFFF VALUE System Handlers 12-15 Priority 0 32 read-write INTSTA Interrupt Control State 0xD04 32 read-write n 0x0 0xFFFFFFFF VALUE Interrupt Control State 0 32 read-write INTTRGI Software Trigger Interrupt Register 0xF00 32 read-write n 0x0 0xFFFFFFFF VALUE Software Trigger Interrupt Register 0 32 read-write INTVEC Vector Table Offset 0xD08 32 read-write n 0x0 0xFFFFFFFF VALUE Vector Table Offset 0 32 read-write STKCAL Systick Calibration Value 0x1C 32 read-write n 0x0 0xFFFFFFFF VALUE Systick Calibration Value 0 32 read-write STKLD Systick Reload Value 0x14 32 read-write n 0x0 0xFFFFFFFF VALUE Systick Reload Value 0 32 read-write STKSTA Systick Control and Status 0x10 32 read-write n 0x0 0xFFFFFFFF VALUE Systick Control and Status 0 32 read-write STKVAL Systick Current Value 0x18 32 read-write n 0x0 0xFFFFFFFF VALUE Systick Current Value 0 32 read-write PMG0 Power Management PMG0 0x4004C000 0x0 0x50 registers n PMG0_VREG_OVR Voltage Regulator (VREG) Overvoltage 6 PMG0_BATT_RANGE Battery Voltage (VBAT) Out of Range 7 CTL1 HPBUCK Control 0x44 32 read-write n 0xA00000 0xFFFFFFFF HPBUCKEN Enable HP Buck 0 1 read-write HPBUCK_LD_MODE HP Buck Load Mode 1 1 read-write HPBUCKLOWLOAD HPBUCK Low load mode is enabled 0 HPBUCKHIGHLOAD HPBUCK High load mode is enabled 1 HPBUCK_LOWPWR_MODE HP Buck Low Power Mode 2 1 read-write LOWPWRDisable HPBUCK Low power mode is disabled 0 LOWPWREnable HPBUCK Low power mode is enabled 1 IEN Power Supply Monitor Interrupt Enable 0x0 32 read-write n 0x0 0xFFFFFFFF IENBAT Interrupt Enable for VBAT Range 10 1 read-write RANGEBAT Battery Monitor Range 8 2 read-write region1 Configure to generate interrupt if VBAT in Region1 0 region2 Configure to generate interrupt if VBAT in Region2 1 region3 Configure to generate interrupt if VBAT in Region3 2 NA NA 3 VBAT Enable Interrupt for VBAT 0 1 read-write VREGOVR Enable Interrupt When VREG Over Voltage (Above 1.32V) 2 1 read-write VREGUNDR Enable Interrupt When VREG Under Voltage (Below 1V) 1 1 read-write PSM_STAT Power Supply Monitor Status 0x4 32 read-write n 0x0 0xFFFFFFFF RANGE1 VBAT Range1 8 1 read-write RANGE2 VBAT Range2 9 1 read-write RANGE3 VBAT Range3 10 1 read-write RORANGE1 VBAT Range1 13 1 read-only batstat1 VBAT NOT in the range specified 0 batstat0 VBAT in the range specified 1 RORANGE2 VBAT Range2 14 1 read-only RORANGE3 VBAT Range3 15 1 read-only VBATUNDR Status Bit Indicating an Alarm That Battery is Below 1.8V 0 1 read-write VREGOVR Status Bit for Alarm Indicating Over Voltage for VREG 2 1 read-write VREGUNDR Status Bit for Alarm Indicating VREG is Below 1V 1 1 read-write WICENACK WIC Enable Acknowledge from Cortex 7 1 read-only PWRKEY Key Protection for PMG_PWRMOD and PMG_SRAMRET 0xC 32 read-write n 0x0 0xFFFFFFFF VALUE Power Control Key 0 16 write-only PWRMOD Power Mode Register 0x8 32 read-write n 0x0 0xFFFFFFFF MODE Power Mode Bits 0 2 read-write FLEXI Flexi Mode 0 HIBERNATE Hibernate Mode 2 SHUTDOWN Shutdown Mode 3 MONVBATN Monitor VBAT During Hibernate Mode 3 1 read-write MONITOR_EN VBAT monitor enabled in PMG block 0 MONITOR_DIS VBAT monitor disabled in PMG block 1 RST_STAT Reset Status 0x40 32 read-write n 0x0 0xFFFFFFFF EXTRST External Reset 1 1 read-write POR Power-on Reset 0 1 read-write PORSRC Power on Reset Source 4 2 read-only FAILSAFE_HV POR triggered because VBAT drops below Fail Safe 0 RST_VBAT POR trigger because VBAT supply (VBAT < 1.7 V) 1 RST_VREG POR triggered because VDD supply (VDD < 1.08 V) 2 FAILSAFE_LV POR triggered because VREG drops below Fail Safe 3 SWRST Software Reset 3 1 read-write WDRST Watchdog Timeout 2 1 read-write SHDN_STAT Shutdown Status Register 0x10 32 read-write n 0x0 0xFFFFFFFF EXTINT0 Interrupt from External Interrupt 0 0 1 read-only EXTINT1 Interrupt from External Interrupt 1 1 1 read-only EXTINT2 Interrupt from External Interrupt 2 2 1 read-only RTC Interrupt from RTC 3 1 read-only SRAMRET Control for Retention SRAM in Hibernate Mode 0x14 32 read-write n 0xFF000000 0xFFFFFFFF HIBERNATE_SRAM_LOAD_MODE Hibernate Mode SRAM Load Mode Control 23 1 read-write RET1 Enable Retention Bank 1 (12 KB) 0 1 read-write RET2 Enable Retention Bank 3 and Bank 4 (32 KB) 1 1 read-write RET3 Enable Retention Bank 5 (32 KB) 8 1 read-write RET4 Enable Retention Bank 6 and Bank 7 (32 KB) 9 1 read-write TRIM Trimming Bits 0x38 32 read-write n 0xA8AA2A2 0xFFFFFFFF hibernate_load_mode Hibernate Mode Load Mode Control 29 3 read-write HIGH_LOAD High hibernate load 0 LOW_LOAD Low hibernate load 7 PMG0_TST Power Management PMG0_TST 0x4004C200 0x0 0x50 registers n CLR_LATCH_GPIOS Clear GPIO After Shutdown Mode 0x68 16 read-write n 0x0 0xFFFFFFFF VALUE Clear the Latches for GPIOs 0 16 write-only FAST_SHT_WAKEUP Fast Shutdown Wake-up Enable 0x74 32 read-write n 0x0 0xFFFFFFFF FAST_SHT_WAKEUP Enables Fast Shutdown Wake-up 0 1 read-write FASTWAKE_DIS Fast shutdown wakeup is disabled 0 FASTWAKE_EN Fast shutdown wakeup is enabled 1 SCRPAD_3V_RD Scratch Pad Saved in Battery Domain 0x70 32 read-write n 0x0 0xFFFFFFFF DATA Reading the Scratch Pad Stored in Shutdown Mode 0 32 read-only SCRPAD_IMG Scratch Pad Image 0x6C 32 read-write n 0x0 0xFFFFFFFF DATA Scratch Image 0 32 read-write SRAM_CTL Control for SRAM Parity and Instruction SRAM 0x60 32 read-write n 0x80000000 0xFFFFFFFF ABTINIT Abort Current Initialization. Self-cleared 15 1 read-write AUTOINIT Automatic Initialization on Wake up from Hibernate Mode 14 1 read-write BNK1EN Enable Initialization 1 1 read-write BNK2EN Enable Initialization 2 1 read-write BNK7EN Enable Initialization 7 1 read-write INSTREN Enables 32kB Instruction SRAM 31 1 read-write PENBNK0 Enable Parity Check 16 1 read-write PENBNK1 Enable Parity Check 17 1 read-write PENBNK2 Enable Parity Check 18 1 read-write PENBNK3 Enable Parity Check 19 1 read-write PENBNK4 Enable Parity Check 20 1 read-write PENBNK5 Enable Parity Check 21 1 read-write PENBNK6 Enable Parity Check 22 1 read-write PENBNK7 Enable Parity Check 23 1 read-write STARTINIT Start Manual Initialization 13 1 read-write SRAM_INITSTAT Initialization Status Register 0x64 32 read-write n 0x0 0xFFFFFFFF BNK0DONE Bank 0 Initialization Status 0 1 read-only NO_BANK0_INIT Bank 0 not initialized 0 BANK0_INIT Bank 0 initialized 1 BNK1DONE Bank 1 Initialization Status 1 1 read-only NO_BANK1_INIT Bank 1 not initialized 0 BANK1_INIT Bank 1 initialized 1 BNK2DONE Bank 2 Initialization Status 2 1 read-only NO_BANK2_INIT Bank 2 not initialized 0 BANK2_INIT Bank 2 initialized 1 BNK3DONE Bank 3 Initialization Status 3 1 read-only NO_BANK3_INIT Bank 3 not initialized 0 BANK3_INIT Bank 3 initialized 1 BNK4DONE Bank 4 Initialization Status 4 1 read-only NO_BANK4_INIT Bank 4 not initialized 0 BANK4_INIT Bank 4 initialized 1 BNK5DONE Bank 5 Initialization Status 5 1 read-only NO_BANK5_INIT Bank 5 not initialized 0 BANK5_INIT Bank 5 initialized 1 BNK6DONE Bank 6 Initialization Status 6 1 read-only NO_BANK6_INIT Bank 6 not initialized 0 BANK6_INIT Bank 6 initialized 1 BNK7DONE Bank 7 Initialization Status 7 1 read-only NO_BANK7_INIT Bank 7 not initialized 0 BANK7_INIT Bank 7 initialized 1 RNG0 Random Number Generator RNG0 0x40040400 0x0 0x100 registers n RNG0_EVT Event 44 CTL RNG Control Register 0x0 16 read-write n 0x0 0xFFFFFFFF EN RNG Enable 0 1 read-write DISABLE Disable the RNG 0 ENABLE Enable the RNG 1 SINGLE Generate a Single Number 3 1 read-write WORD Buffer Word 0 SINGLE Single Byte 1 DATA RNG Data Register 0xC 32 read-write n 0x0 0xFFFFFFFF BUFF Buffer for RNG Data 8 24 read-only VALUE Value of the CRC Accumulator 0 8 read-only LEN RNG Sample Length Register 0x4 16 read-write n 0x3400 0xFFFFFFFF PRESCALE Prescaler for the Sample Counter 12 4 read-write RELOAD Reload Value for the Sample Counter 0 12 read-write OSCCNT Oscillator Count 0x10 32 read-write n 0x0 0xFFFFFFFF VALUE Oscillator Count 0 28 read-only OSCDIFF0 Oscillator Difference 0x14 8 read-write n 0x0 0xFFFFFFFF DELTA Oscillator Count Difference 0 8 read-only OSCDIFF1 Oscillator Difference 0x15 8 read-write n 0x0 0xFFFFFFFF DELTA Oscillator Count Difference 0 8 read-only OSCDIFF2 Oscillator Difference 0x16 8 read-write n 0x0 0xFFFFFFFF DELTA Oscillator Count Difference 0 8 read-only OSCDIFF3 Oscillator Difference 0x17 8 read-write n 0x0 0xFFFFFFFF DELTA Oscillator Count Difference 0 8 read-only OSCDIFF[0] Oscillator Difference 0x28 8 read-write n 0x0 0xFFFFFFFF DELTA Oscillator Count Difference 0 8 read-only OSCDIFF[1] Oscillator Difference 0x3D 8 read-write n 0x0 0xFFFFFFFF DELTA Oscillator Count Difference 0 8 read-only OSCDIFF[2] Oscillator Difference 0x53 8 read-write n 0x0 0xFFFFFFFF DELTA Oscillator Count Difference 0 8 read-only OSCDIFF[3] Oscillator Difference 0x6A 8 read-write n 0x0 0xFFFFFFFF DELTA Oscillator Count Difference 0 8 read-only STAT RNG Status Register 0x8 16 read-write n 0x0 0xFFFFFFFF RNRDY Random Number Ready 0 1 read-write STUCK Sampled Data Stuck High or Low 1 1 read-write RTC0 Real-Time Clock RTC0 0x40001000 0x0 0x100 registers n RTC0_EVT Event 8 ALM0 RTC Alarm 0 0x14 16 read-write n 0xFFFF 0xFFFFFFFF VALUE Lower 16 Prescaled (i.e. Non-Fractional) Bits of the RTC Alarm Target Time 0 16 read-write ALM1 RTC Alarm 1 0x18 16 read-write n 0xFFFF 0xFFFFFFFF VALUE Upper 16 Prescaled (Non-Fractional) Bits of the RTC Alarm Target Time 0 16 read-write ALM2 RTC Alarm 2 0x44 16 read-write n 0x0 0xFFFFFFFF VALUE Fractional Bits of the Alarm Target Time 0 15 read-write CNT0 RTC Count 0 0xC 16 read-write n 0x0 0xFFFFFFFF VALUE Lower 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count 0 16 read-write CNT1 RTC Count 1 0x10 16 read-write n 0x0 0xFFFFFFFF VALUE Upper 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count 0 16 read-write CNT2 RTC Count 2 0x40 16 read-write n 0x0 0xFFFFFFFF VALUE Fractional Bits of the RTC Real-Time Count 0 15 read-only CR0 RTC Control 0 0x0 16 read-write n 0x3C4 0xFFFFFFFF ALMEN Enable the RTC Alarm (Absolute) Operation 1 1 read-write ALMINTEN Enable ALMINT Sourced Alarm Interrupts to the CPU 2 1 read-write CNTEN Global Enable for the RTC 0 1 read-write ISOINTEN Enable ISOINT Sourced Interrupts to the CPU When Isolation of the RTC Power Domain is Activated and Subsequently De-activated 12 1 read-write MOD60ALM Periodic, Modulo-60 Alarm Time in Prescaled RTC Time Units Beyond a Modulo-60 Boundary 5 6 read-write MOD60ALMEN Enable RTC Modulo-60 Counting of Time Past a Modulo-60 Boundary 4 1 read-write MOD60ALMINTEN Enable Periodic Modulo-60 RTC Alarm Sourced Interrupts to the CPU 11 1 read-write TRMEN Enable RTC Digital Trimming 3 1 read-write WPNDERRINTEN Enable Write Pending Error Sourced Interrupts to the CPU When an RTC Register-write Pending Error Occurs 13 1 read-write WPNDINTEN Enable Write Pending Sourced Interrupts to the CPU 15 1 read-write WSYNCINTEN Enable Write Synchronization Sourced Interrupts to the CPU 14 1 read-write CR1 RTC Control 1 0x28 16 read-write n 0x1E0 0xFFFFFFFF CNTINTEN Enable for the RTC Count Interrupt Source 0 1 read-write CNTMOD60ROLLINTEN Enable for the RTC Modulo-60 Count Roll-Over Interrupt Source 4 1 read-write CNTROLLINTEN Enable for the RTC Count Roll-Over Interrupt Source, in SR2:RTCCNTROLLINT 3 1 read-write PRESCALE2EXP Prescale Power of 2 Division Factor for the RTC Base Clock 5 4 read-write PSINTEN Enable for the Prescaled, Modulo-1 Interrupt Source, in SR2:RTCPSINT 1 1 read-write TRMINTEN Enable for the RTC Trim Interrupt Source, in SR2:RTCTRMINT 2 1 read-write CR2IC RTC Control 2 for Configuring Input Capture Channels 0x4C 16 read-write n 0x83A0 0xFFFFFFFF IC0EN Enable for the RTC Input Capture Channel 0 0 1 read-write IC0IRQEN Interrupt Enable for the RTC Input Capture Channel 0 10 1 read-write IC0LH Polarity of the Active-Going Capture Edge for the RTC Input Capture Channel 0 5 1 read-write IC2EN Enable for the RTC Input Capture Channel 2 2 1 read-write IC2IRQEN Interrupt Enable for the RTC Input Capture Channel 2 12 1 read-write IC2LH Polarity of the Active-going Capture Edge for the Input Capture Channel 2 7 1 read-write IC3EN Enable for the RTC Input Capture Channel 3 3 1 read-write IC3IRQEN Interrupt Enable for the RTC Input Capture Channel 3 13 1 read-write IC3LH Polarity of the Active-going Capture Edge for the Input Capture Channel 3 8 1 read-write IC4EN Enable for the RTC Input Capture Channel 4 4 1 read-write IC4IRQEN Interrupt Enable for the RTC Input Capture Channel 4 14 1 read-write IC4LH Polarity of the Active-going Capture Edge for the Input Capture Channel 4 9 1 read-write ICOWUSEN Enable Overwrite of Unread Snapshots for All Input Capture Channels 15 1 read-write CR3SS RTC Control 3 for Configuring SensorStrobe Channel 0x50 16 read-write n 0x0 0xFFFFFFFF SS1EN Enable for SensorStrobe Channel 1 1 1 read-write SS1FEIRQEN Falling Edge Interrupt Enable for the SensorStrobe Channel 1 5 1 read-write SS1IRQEN Interrupt Enable for SensorStrobe Channel 1 9 1 read-write SS2EN Enable for the SensorStrobe Channel 2 2 1 read-write SS2FEIRQEN Falling Edge Interrupt Enable for the SensorStrobe Channel 2 6 1 read-write SS2IRQEN Posedge EdgeInterrupt Enable for the SensorStrobe Channel 2 10 1 read-write SS3EN Enable for the SensorStrobe Channel 3 3 1 read-write SS3FEIRQEN Falling Edge Interrupt Enable for the SensorStrobe Channel 3 7 1 read-write SS3IRQEN Posedge EdgeInterrupt Enable for the SensorStrobe Channel 3 11 1 read-write SS4EN Enable for the SensorStrobe Channel 4 4 1 read-write SS4FEIRQEN Falling Edge Interrupt Enable for the SensorStrobe Channel 4 8 1 read-write SS4IRQEN Posedge EdgeInterrupt Enable for the SensorStrobe Channel 4 12 1 read-write CR4SS RTC Control 4 for Configuring SensorStrobe Channel 0x54 16 read-write n 0x0 0xFFFFFFFF SS1ARLEN Enable for Fine Control on SensorStrobe Channel 1 Period and Duty Cycle 9 1 read-write SS1MSKEN Enable for Thermometer-Code Masking of the SensorStrobe Channel 1 1 1 read-write NO_MSK Do not apply a mask to SensorStrobe Channel 1 Register 0 THERM_MSK Apply thermometer decoded mask 1 SS1POL SensorSTrobe Channel 1 Polarity Control 5 1 read-write SS2ARLEN Enable for Fine Control on SensorStrobe Channel 2 Period and Duty Cycle 10 1 read-write SS2MSKEN Enable for Thermometer-Code Masking of the SensorStrobe Channel 2 2 1 read-write SS2POL SensorStrobe Channel 2 Polarity Control 6 1 read-write SS3ARLEN Enable for Fine Control on SensorStrobe Channel 3 Period and Duty Cycle 11 1 read-write SS3MSKEN Enable for Thermometer-Code Masking of the SensorStrobe Channel 3 3 1 read-write SS3POL SensorStrobe Channel 3 Polarity Control 7 1 read-write SS4MSKEN Enable for Thermometer-Code Masking of the SensorStrobe Channel 4 4 1 read-write SS4POL SensorStrobe Channel 4 Polarity Control 8 1 read-write CR5SSS RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling 0xC4 16 read-write n 0x0 0xFFFFFFFF SS1SMPEN GPIO Input Sample Enable for SensorStrobe Channel 1 0 3 read-write SS1SMPMTCHIRQEN Sample Activity Interrupt Enable for SensorStrobe Channel 1 3 1 read-write SS2SMPEN GPIO Input Sample Enable for SensorStrobe Channel 2 4 3 read-write SS2SMPMTCHIRQEN Sample Activity Interrupt Enable for SensorStrobe Channel 2 7 1 read-write SS3SMPEN GPIO Input Sample Enable for SensorStrobe Channel 3 8 3 read-write SS3SMPMTCHIRQEN Sample Activity Interrupt Enable for SensorStrobe Channel 3 11 1 read-write CR6SSS RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge 0xC8 16 read-write n 0x0 0xFFFFFFFF SS1SMPONFE GPIO Sample Around Falling Edge of SensorStrobe Channel 1 0 2 read-write SS1NOFES No sampling of input around falling edge 0 SS1BFES Input sampled one clock cycle before falling edge of the SensorStrobe channel 1 1 SS1FES Input sampled at falling edge of the SensorStrobe channel 1 2 SS1AFES Input sampled one clock cycle after falling edge of the SensorStrobe channel 1 3 SS1SMPONRE GPIO Sample Around Rising Edge of SensorStrobe Channel 1 2 2 read-write SS1NORES No sampling of input around rising edge 0 SS1BRES Input sampled one clock cycle before rising edge of the SensorStrobe channel 1 1 SS1RES Input sampled at rising edge of the SensorStrobe channel 1 2 SS1ARES Input sampled one clock cycle after rising edge of the SensorStrobe channel 1 3 SS2SMPONFE GPIO Sample Around Falling Edge of SensorStrobe Channel 2 4 2 read-write SS2NOFES No sampling of input around falling edge 0 SS2BFES Input sampled one clock cycle before falling edge of the SensorStrobe channel 2 1 SS2FES Input sampled at falling edge of the SensorStrobe channel 2 2 SS2AFES Input sampled one clock cycle after falling edge of the SensorStrobe channel 2 3 SS2SMPONRE GPIO Sample Around Rising Edge of SensorStrobe Channel 2 6 2 read-write SS2NORES No sampling of input around rising edge 0 SS2BRES Input sampled one clock cycle before rising edge of the SensorStrobe channel 2 1 SS2RES Input sampled at rising edge of the SensorStrobe channel 2 2 SS2ARES Input sampled one clock cycle after rising edge of the SensorStrobe channel 2 3 SS3SMPONFE GPIO Sample Around Falling Edge of SensorStrobe Channel 3 8 2 read-write SS3NOFES No sampling of input around falling edge 0 SS3BFES Input sampled one clock cycle before falling edge of the SensorStrobe channel 3 1 SS3FES Input sampled at falling edge of the SensorStrobe channel 3 2 SS3AFES Input sampled one clock cycle after falling edge of the SensorStrobe channel 3 3 SS3SMPONRE GPIO Sample Around Rising Edge of SensorStrobe Channel 3 10 2 read-write SS3NORES No sampling of input around rising edge 0 SS3BRES Input sampled one clock cycle before rising edge of the SensorStrobe channel 3 1 SS3RES Input sampled at rising edge of the SensorStrobe channel 3 2 SS3ARES Input sampled one clock cycle after rising edge of the SensorStrobe channel 3 3 CR7SSS RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity 0xCC 16 read-write n 0x0 0xFFFFFFFF SS1SMPEXP Expected GPIO Sample for SensorStrobe Channel 1 0 3 read-write SS1SMPPTRN Sample Activity Selection for SensorStrobe Channel 1 3 2 read-write SS1SMPCHNG Current GPIO sample is not same as previous sample 0 SS1SMPSAME Current GPIO sample is same as previous sample 1 SS1SMPMTCH Current GPIO sample is same as expected sample 2 SS1SMPNOMTCH Current GPIO sample is not same as expected sample 3 SS2SMPEXP Expected GPIO Sample for SensorStrobe Channel 2 5 3 read-write SS2SMPPTRN Sample Activity Selection for SensorStrobe Channel 2 8 2 read-write SS2SMPCHNG Current GPIO sample is not same as previous sample 0 SS2SMPSAME Current GPIO sample is same as previous sample 1 SS2SMPMTCH Current GPIO sample is same as expected sample 2 SS2SMPNOMTCH Current GPIO sample is not same as expected sample 3 SS3SMPEXP Expected GPIO Sample for SensorStrobe Channel 3 10 3 read-write SS3SMPPTRN Sample Activity Selection for SensorStrobe Channel 3 13 2 read-write SS3SMPCHNG Current GPIO sample is not same as previous sample 0 SS3SMPSAME Current GPIO sample is same as previous sample 1 SS3SMPMTCH Current GPIO sample is same as expected sample 2 SS3SMPNOMTCH Current GPIO sample is not same as expected sample 3 FRZCNT RTC Freeze Count 0x90 16 read-write n 0x0 0xFFFFFFFF FRZCNT RTC Freeze Count. Coherent, Triple 16-Bit Read of the 47-Bit RTC Count 0 16 read-only GPMUX0 RTC GPIO Pin Mux Control Register 0 0xE0 16 read-write n 0x4688 0xFFFFFFFF SS1GPIN0SEL GPIO Mux Selection for SensorStrobe Channel 1 Input0 0 3 read-write SS1GPIN1SEL GPIO Mux Selection for SensorStrobe Channel 1 Input 1 3 3 read-write SS1GPIN2SEL GPIO Mux Selection for SensorStrobe Channel 1 Input 2 6 3 read-write SS2GPIN0SEL GPIO Mux Selection for SensorStrobe Channel 2 Input 0 9 3 read-write SS2GPIN1SEL GPIO Mux Selection for SensorStrobe Channel 2 Input 1 12 3 read-write GPMUX1 RTC GPIO Pin Mux Control Register 1 0xE4 16 read-write n 0x1F5 0xFFFFFFFF SS1DIFFOUT Differential SensorStrobe Out Option for SensorStrobe Channel 1 14 1 read-write SS2GPIN2SEL GPIO Mux Selection for SensorStrobe Channel 2 Input 2 0 3 read-write SS3DIFFOUT Differential SensorStrobe Out Option for SensorStrobe Channel 3 15 1 read-write SS3GPIN0SEL GPIO Mux Selection for SensorStrobe Channel 3 Input 0 3 3 read-write SS3GPIN1SEL GPIO Mux Selection for SensorStrobe Channel 3 Input 1 6 3 read-write SS3GPIN2SEL GPIO Mux Selection for SensorStrobe Channel 3 Input 2 9 3 read-write GWY RTC Gateway 0x20 16 read-write n 0x0 0xFFFFFFFF SWKEY Software-keyed Command Issued by the CPU 0 16 write-only IC2 RTC Input Capture Channel 2 0x64 16 read-write n 0x0 0xFFFFFFFF IC2 RTC Input Capture Channel 2 0 16 read-only IC3 RTC Input Capture Channel 3 0x68 16 read-write n 0x0 0xFFFFFFFF IC3 RTC Input Capture Channel 3 0 16 read-only IC4 RTC Input Capture Channel 4 0x6C 16 read-write n 0x0 0xFFFFFFFF IC4 RTC Input Capture Channel 4 0 16 read-only MOD RTC Modulo 0x3C 16 read-write n 0x40 0xFFFFFFFF CNT0_4TOZERO Mirror of CNT0[4:0] 11 5 read-only CNTMOD60 Modulo-60 Value of the RTC Count: CNT1 and CNT0 0 6 read-only INCR Most Recent Increment Value Added to the RTC Count in CNT1 and CNT0 6 4 read-only TRMBDY Trim Boundary Indicator 10 1 read-only SNAP0 RTC Snapshot 0 0x30 16 read-write n 0x0 0xFFFFFFFF VALUE Constituent Part of the 47-bit Input Capture Channel 0, Containing a Sticky Snapshot of CNT0 0 16 read-only SNAP1 RTC Snapshot 1 0x34 16 read-write n 0x0 0xFFFFFFFF VALUE Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT1 0 16 read-only SNAP2 RTC Snapshot 2 0x38 16 read-write n 0x0 0xFFFFFFFF VALUE Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT2 0 15 read-only SR0 RTC Status 0 0x4 16 read-write n 0x3F80 0xFFFFFFFF ALMINT Alarm Interrupt Source 1 1 read-write ISOENB Visibility of 32kHz Sourced Registers 14 1 read-only ISOINT RTC Power-Domain Isolation Interrupt Source 3 1 read-write MOD60ALMINT Modulo-60 RTC Alarm Interrupt Source 2 1 read-write WPNDERRINT Write Pending Error Interrupt Source 4 1 read-write WPNDINT Write Pending Interrupt 6 1 read-write WSYNCALM0 Synchronisation Status of Posted Writes to ALM0 11 1 read-only WSYNCALM1 Synchronisation Status of Posted Writes to ALM1 12 1 read-only WSYNCCNT0 Synchronisation Status of Posted Writes to CNT0 9 1 read-only WSYNCCNT1 Synchronisation Status of Posted Writes to CNT1 10 1 read-only WSYNCCR0 Synchronisation Status of Posted Writes to CR0 7 1 read-only WSYNCINT Write Synchronisation Interrupt 5 1 read-write WSYNCSR0 Synchronisation Status of Posted Writes to SR0 8 1 read-only WSYNCTRM Synchronisation Status of Posted Writes to TRM 13 1 read-only SR1 RTC Status 1 0x8 16 read-write n 0x78 0xFFFFFFFF WPNDALM0 Pending Status of Posted Writes to ALM0 11 1 read-only WPNDALM1 Pending Status of Posted Writes to ALM1 12 1 read-only WPNDCNT0 Pending Status of Posted Writes to CNT0 9 1 read-only WPNDCNT1 Pending Status of Posted Writes to CNT1 10 1 read-only WPNDCR0 Pending Status of Posted Writes to CR0 7 1 read-only WPNDSR0 Pending Status of Posted Clearances of Interrupt Sources in SR0 8 1 read-only WPNDTRM Pending Status of Posted Writes to TRM 13 1 read-only SR2 RTC Status 2 0x2C 16 read-write n 0xC000 0xFFFFFFFF CNTINT RTC Count Interrupt Source 0 1 read-write CNTMOD60ROLL RTC Count Modulo-60 Roll-Over 6 1 read-only CNTMOD60ROLLINT RTC Modulo-60 Count Roll-Over Interrupt Source 4 1 read-write CNTROLL RTC Count Roll-Over 5 1 read-only CNTROLLINT RTC Count Roll-Over Interrupt Source 3 1 read-write PSINT RTC Prescaled, Modulo-1 Boundary Interrupt Source 1 1 read-write TRMBDYMIR Mirror of MOD:RTCTRMBDY 7 1 read-only TRMINT RTC Trim Interrupt Source 2 1 read-write WPNDALM2MIR Pending Status of Posted Writes to ALM2 13 1 read-only WPNDCR1MIR Pending Status of Posted Writes to CR1 12 1 read-only WSYNCALM2MIR Synchronization Status of Posted Writes to ALM2 15 1 read-only WSYNCCR1MIR Synchronization Status of Posted Writes to CR1 14 1 read-only SR3 RTC Status 3 0x48 16 read-write n 0x0 0xFFFFFFFF ALMINTMIR Read-only Mirror of the SR0:ALMINT Interrupt Source 13 1 read-only IC0IRQ Sticky Interrupt Source for the RTC Input Capture Channel 0 0 1 read-write IC2IRQ Sticky Interrupt Source for the RTC Input Capture Channel 2 2 1 read-write IC3IRQ Sticky Interrupt Source for the RTC Input Capture Channel 3 3 1 read-write IC4IRQ Sticky Interrupt Source for the RTC Input Capture Channel 4 4 1 read-write SS1FEIRQ Sticky Interrupt Source for the SensorStrobe Channel 1 Falling Edge 5 1 read-write SS1IRQ Sticky Interrupt Source for SensorStrobe Channel 1 9 1 read-write SS2FEIRQ Sticky Interrupt Source for the SensorStrobe Channel 2 Falling Edge 6 1 read-write SS2IRQ Sticky Interrupt Source for the SensorStrobe Channel 2 10 1 read-write SS3FEIRQ Sticky Interrupt Source for the SensorStrobe Channel 3 Falling Edge 7 1 read-write SS3IRQ Sticky Interrupt Source for the SensorStrobe Channel 3 11 1 read-write SS4FEIRQ Sticky Interrupt Source for the SensorStrobe Channel 4 Falling Edge 8 1 read-write SS4IRQ Sticky Interrupt Source for the SensorStrobe Channel 4 12 1 read-write SR4 RTC Status 4 0x80 16 read-write n 0xF7DF 0xFFFFFFFF RSYNCIC0 Synchronization Status of Posted Reads of RTC Input Channel 0 10 1 read-only RSYNCIC2 Synchronization Status of Posted Reads of RTC Input Channel 2 12 1 read-only RSYNCIC3 Synchronization Status of Posted Reads of RTC Input Channel 3 13 1 read-only RSYNCIC4 Synchronization Status of Posted Reads of RTC Input Channel 4 14 1 read-only WSYNCCR2IC Synchronization Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register 1 1 read-only WSYNCCR3SS Synchronization Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register 2 1 read-only WSYNCCR4SS Synchronization Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register 3 1 read-only WSYNCSR3 Synchronisation Status of Posted Writes to SR3 0 1 read-only WSYNCSS1 Synchronization Status of Posted Writes to SensorStrobe Channel 1 6 1 read-only WSYNCSS2 Synchronization Status of Posted Writes to SensorStrobe Channel 2 7 1 read-only WSYNCSS3 Synchronization Status of Posted Writes to SensorStrobe Channel 3 8 1 read-only WSYNCSS4 Synchronization Status of Posted Writes to SensorStrobe Channel 4 9 1 read-only WSYNCSSMSK Synchronization Status of Posted Writes to Masks for SensorStrobe Channel Register 4 1 read-only WSYNCSSMSKOT Synchronization Status of Posted Reads Writes to Mask for SensorStrobe Channels on Time Control Register 15 1 read-only SR5 RTC Status 5 0x84 16 read-write n 0x0 0xFFFFFFFF RPENDIC0 Pending Status of Posted Reads of Input Capture Channel 0 10 1 read-only RPENDIC2 Pending Status of Posted Reads of IC2 12 1 read-only RPENDIC3 Pending Status of Posted Reads of IC3 13 1 read-only RPENDIC4 Pending Status of Posted Reads of IC4 14 1 read-only WPENDCR2IC Pending Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register 1 1 read-only WPENDCR3SS Pending Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register 2 1 read-only WPENDCR4SS Pending Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register 3 1 read-only WPENDSR3 Pending Status of Posted Clearances of Interrupt Sources in RTC Status 3 Register 0 1 read-only WPENDSS1 Pending Status of Posted Writes to SensorStrobe Channel 1 6 1 read-only WPENDSS2 Pending Status of Posted Writes to SensorStrobe Channel 2 7 1 read-only WPENDSS3 Pending Status of Posted Writes to SensorStrobe Channel 3 8 1 read-only WPENDSS4 Pending Status of Posted Writes to SensorStrobe Channel 4 9 1 read-only WPENDSSMSK Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register 4 1 read-only WPENDSSMSKOT Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register 15 1 read-only SR6 RTC Status 6 0x88 16 read-write n 0x7900 0xFFFFFFFF FRZCNTPTR Pointer for the Triple-Read Sequence of FRZCNT 9 2 read-only IC0SNAP Confirmation That RTC Snapshot 0, 1, 2 Registers Reflect the Value of Input-Capture Channel RTC Input Capture Channel 0 8 1 read-only IC0UNR Sticky Unread Status of the Input Capture Channel 0 0 1 read-only IC2UNR Sticky Unread Status of the Input Capture Channel 2 2 1 read-only IC3UNR Sticky Unread Status of the Input Capture Channel 3 3 1 read-only IC4UNR Sticky Unread Status of the Input Capture Channel 4 4 1 read-only SR7 RTC Status 7 0xD0 16 read-write n 0x0 0xFFFFFFFF SS1OUT Output Value for SensorStrobe Channel 1 12 1 read-only SS1SMP Latest GPIO Sample for SensorStrobe Channel 1 0 3 read-only SS1SMPMTCHIRQ Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 1 3 1 read-write SS2OUT Output Value for SensorStrobe Channel 2 13 1 read-only SS2SMP Latest GPIO Sample for SensorStrobe Channel 2 4 3 read-only SS2SMPMTCHIRQ Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 2 7 1 read-write SS3OUT Output Value for SensorStrobe Channel 3 14 1 read-only SS3SMP Latest GPIO Sample for SensorStrobe Channel 3 8 3 read-only SS3SMPMTCHIRQ Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 3 11 1 read-write SS4OUT Output Value for SensorStrobe Channel 4 15 1 read-only SR8 RTC Status 8 0xD4 16 read-write n 0x3F77 0xFFFFFFFF WSYNCCR5SSS Synchronisation Status of Posted Writes to Control 5 for Configuring SensorStrobe Channel Register 8 1 read-only WSYNCCR6SSS Synchronisation Status of Posted Writes to Control 6 for Configuring SensorStrobe Channel Register 9 1 read-only WSYNCCR7SSS Synchronisation Status of Posted Writes to Control 7 for Configuring SensorStrobe Channel Register 10 1 read-only WSYNCGPMUX0 Synchronisation Status of Posted Writes to GPIO Pin Mux Control Register 0 12 1 read-only WSYNCGPMUX1 Synchronisation Status of Posted Writes to GPIO Pin Mux Control Register 1 13 1 read-only WSYNCSR7 Synchronisation Status of Posted Writes to Status 7 Register 11 1 read-only WSYNCSS1HIGHDUR Synchronisation Status of Posted Writes to SensorStrobe Channel 1 High Duration Register 4 1 read-only WSYNCSS1LOWDUR Synchronisation Status of Posted Writes to SensorStrobe Channel 1 Low Duration Register 0 1 read-only WSYNCSS2HIGHDUR Synchronisation Status of Posted Writes to SensorStrobe Channel 2 High Duration Register 5 1 read-only WSYNCSS2LOWDUR Synchronisation Status of Posted Writes to SensorStrobe Channel 2 Low Duration Register 1 1 read-only WSYNCSS3HIGHDUR Synchronisation Status of Posted Writes to SensorStrobe Channel 3 High Duration Register 6 1 read-only WSYNCSS3LOWDUR Synchronisation Status of Posted Writes to SensorStrobe Channel 3 Low Duration Register 2 1 read-only SR9 RTC Status 9 0xD8 16 read-write n 0x0 0xFFFFFFFF WPENDCR5SSS Pending Status of Posted Writes to Control 5 for Configuring SensorStrobe Channel Register 8 1 read-only WPENDCR6SSS Pending Status of Posted Writes to Control 6 for Configuring SensorStrobe Channel Register 9 1 read-only WPENDCR7SSS Pending Status of Posted Writes to Control 7 for Configuring SensorStrobe Channel Register 10 1 read-only WPENDGPMUX0 Pending Status of Posted Writes to GPMUX0 12 1 read-only WPENDGPMUX1 Pending Status of Posted Writes to GPMUX1 13 1 read-only WPENDSR7 Pending Status of Posted Writes to SR7 11 1 read-only WPENDSS1HIGHDUR Pending Status of Posted Writes to SensortStrobe Channel 1 High Duration Register 4 1 read-only WPENDSS1LOWDUR Pending Status of Posted Writes to SensortStrobe Channel 1 Low Duration Register 0 1 read-only WPENDSS2HIGHDUR Pending Status of Posted Writes to SensortStrobe Channel 2 High Duration Register 5 1 read-only WPENDSS2LOWDUR Pending Status of Posted Writes to SensortStrobe Channel 2 Low Duration Register 1 1 read-only WPENDSS3HIGHDUR Pending Status of Posted Writes to SensortStrobe Channel 3 High Duration Register 6 1 read-only WPENDSS3LOWDUR Pending Status of Posted Writes to SensortStrobe Channel 3 Low Duration Register 2 1 read-only SS1 RTC SensorStrobe Channel 1 0x70 16 read-write n 0x8000 0xFFFFFFFF SS1 SensorStrobe Channel 1 0 16 read-write SS1HIGHDUR RTC Auto-Reload High Duration for SensorStrobe Channel 1 0xB0 16 read-write n 0x8000 0xFFFFFFFF SS1HIGHDUR High Duration for SensorStrobe Channel 1 0 16 read-write SS1LOWDUR RTC Auto-Reload Low Duration for SensorStrobe Channel 1 0xA0 16 read-write n 0x8000 0xFFFFFFFF SS1LOWDUR Low Duration for SensorStrobe Channel 1 0 16 read-write SS1TGT RTC SensorStrobe Channel 1 Target 0x8C 16 read-write n 0x8000 0xFFFFFFFF SS1TGT Current Target Value for the SensorStrobe Channel 1 0 16 read-only SS2 RTC SensorStrobe Channel 2 0x74 16 read-write n 0x8000 0xFFFFFFFF SS2 SensorStrobe Channel 2 0 16 read-write SS2HIGHDUR RTC Auto-Reload High Duration for SensorStrobe Channel 2 0xB4 16 read-write n 0x8000 0xFFFFFFFF SS2HIGHDUR High Duration for SensorStrobe Channel 2 0 16 read-write SS2LOWDUR RTC Auto-Reload Low Duration for SensorStrobe Channel 2 0xA4 16 read-write n 0x8000 0xFFFFFFFF SS2LOWDUR Low Duration for SensorStrobe Channel 2 0 16 read-write SS2TGT RTC SensorStrobe Channel 2 Target 0x94 16 read-write n 0x8000 0xFFFFFFFF SS2TGT Current, Cumulative Target Time for SensorStrobe Channel 2, Taking Account of Any Auto-reloading 0 16 read-only SS3 RTC SensorStrobe Channel 3 0x78 16 read-write n 0x8000 0xFFFFFFFF SS3 SensorStrobe Channel 3 0 16 read-write SS3HIGHDUR RTC Auto-Reload High Duration for SensorStrobe Channel 3 0xB8 16 read-write n 0x8000 0xFFFFFFFF SS3HIGHDUR High Duration for SensorStrobe Channel 3 0 16 read-write SS3LOWDUR RTC Auto-Reload Low Duration for SensorStrobe Channel 3 0xA8 16 read-write n 0x8000 0xFFFFFFFF SS3LOWDUR Low Duration for SensorStrobe Channel 3 0 16 read-write SS3TGT RTC SensorStrobe Channel 3 Target 0x98 16 read-write n 0x8000 0xFFFFFFFF SS3TGT Current, Cumulative Target Time for SensorStrobe Channel 3, Taking Account of Any Auto-reloading 0 16 read-only SS4 RTC SensorStrobe Channel 4 0x7C 16 read-write n 0x8000 0xFFFFFFFF SS4 SensorStrobe Channel 4 0 16 read-write SSMSK RTC Mask for SensorStrobe Channel 0x58 16 read-write n 0x0 0xFFFFFFFF SS1MSK Concatenation of Thermometer-Encoded Masks for the 16-bit SensorStrobe Channels 0 4 read-write SS2MSK SensorStrobe Channel 2 Period Control 4 4 read-write SS3MSK SensorStrobe Channel 3 Period Control 8 4 read-write SS4MSK SensorStrobe Channel 4 Period Control 12 4 read-write SSMSKOT RTC Masks for SensorStrobe Channels on Time Control 0xC0 16 read-write n 0x0 0xFFFFFFFF SS1MSKOT Concatenation of Thermometer-encoded Masks for the 16-bit SensorStrobe Channels 0 4 read-write SS2MSKOT SensorStrobe Channel 2 on Time Control 4 4 read-write SS3MSKOT SensorStrobe Channel 3 on Time Control 8 4 read-write SS4MSKOT SensorStrobe Channel 4 on Time Control 12 4 read-write TRM RTC Trim 0x1C 16 read-write n 0x398 0xFFFFFFFF ADD Trim Polarity 3 1 read-write IVL Trim Interval in Prescaled RTC Time Units 4 2 read-write IVL2EXPMIN Minimum Power-of-two Interval of Prescaled RTC Time Units Which TRM:TRMIVL TRMIVL Can Select 6 4 read-write VALUE Trim Value in Prescaled RTC Time Units to Be Added or Subtracted from the RTC Count at the End of a Periodic Interval Selected by TRM:TRMIVL 0 3 read-write RTC1 Real-Time Clock RTC0 0x40001400 0x0 0x100 registers n RTC1_EVT Event 0 ALM0 RTC Alarm 0 0x14 16 read-write n 0xFFFF 0xFFFFFFFF VALUE Lower 16 Prescaled (i.e. Non-Fractional) Bits of the RTC Alarm Target Time 0 16 read-write ALM1 RTC Alarm 1 0x18 16 read-write n 0xFFFF 0xFFFFFFFF VALUE Upper 16 Prescaled (Non-Fractional) Bits of the RTC Alarm Target Time 0 16 read-write ALM2 RTC Alarm 2 0x44 16 read-write n 0x0 0xFFFFFFFF VALUE Fractional Bits of the Alarm Target Time 0 15 read-write CNT0 RTC Count 0 0xC 16 read-write n 0x0 0xFFFFFFFF VALUE Lower 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count 0 16 read-write CNT1 RTC Count 1 0x10 16 read-write n 0x0 0xFFFFFFFF VALUE Upper 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count 0 16 read-write CNT2 RTC Count 2 0x40 16 read-write n 0x0 0xFFFFFFFF VALUE Fractional Bits of the RTC Real-Time Count 0 15 read-only CR0 RTC Control 0 0x0 16 read-write n 0x3C4 0xFFFFFFFF ALMEN Enable the RTC Alarm (Absolute) Operation 1 1 read-write ALMINTEN Enable ALMINT Sourced Alarm Interrupts to the CPU 2 1 read-write CNTEN Global Enable for the RTC 0 1 read-write ISOINTEN Enable ISOINT Sourced Interrupts to the CPU When Isolation of the RTC Power Domain is Activated and Subsequently De-activated 12 1 read-write MOD60ALM Periodic, Modulo-60 Alarm Time in Prescaled RTC Time Units Beyond a Modulo-60 Boundary 5 6 read-write MOD60ALMEN Enable RTC Modulo-60 Counting of Time Past a Modulo-60 Boundary 4 1 read-write MOD60ALMINTEN Enable Periodic Modulo-60 RTC Alarm Sourced Interrupts to the CPU 11 1 read-write TRMEN Enable RTC Digital Trimming 3 1 read-write WPNDERRINTEN Enable Write Pending Error Sourced Interrupts to the CPU When an RTC Register-write Pending Error Occurs 13 1 read-write WPNDINTEN Enable Write Pending Sourced Interrupts to the CPU 15 1 read-write WSYNCINTEN Enable Write Synchronization Sourced Interrupts to the CPU 14 1 read-write CR1 RTC Control 1 0x28 16 read-write n 0x1E0 0xFFFFFFFF CNTINTEN Enable for the RTC Count Interrupt Source 0 1 read-write CNTMOD60ROLLINTEN Enable for the RTC Modulo-60 Count Roll-Over Interrupt Source 4 1 read-write CNTROLLINTEN Enable for the RTC Count Roll-Over Interrupt Source, in SR2:RTCCNTROLLINT 3 1 read-write PRESCALE2EXP Prescale Power of 2 Division Factor for the RTC Base Clock 5 4 read-write PSINTEN Enable for the Prescaled, Modulo-1 Interrupt Source, in SR2:RTCPSINT 1 1 read-write TRMINTEN Enable for the RTC Trim Interrupt Source, in SR2:RTCTRMINT 2 1 read-write CR2IC RTC Control 2 for Configuring Input Capture Channels 0x4C 16 read-write n 0x83A0 0xFFFFFFFF IC0EN Enable for the RTC Input Capture Channel 0 0 1 read-write IC0IRQEN Interrupt Enable for the RTC Input Capture Channel 0 10 1 read-write IC0LH Polarity of the Active-Going Capture Edge for the RTC Input Capture Channel 0 5 1 read-write IC2EN Enable for the RTC Input Capture Channel 2 2 1 read-write IC2IRQEN Interrupt Enable for the RTC Input Capture Channel 2 12 1 read-write IC2LH Polarity of the Active-going Capture Edge for the Input Capture Channel 2 7 1 read-write IC3EN Enable for the RTC Input Capture Channel 3 3 1 read-write IC3IRQEN Interrupt Enable for the RTC Input Capture Channel 3 13 1 read-write IC3LH Polarity of the Active-going Capture Edge for the Input Capture Channel 3 8 1 read-write IC4EN Enable for the RTC Input Capture Channel 4 4 1 read-write IC4IRQEN Interrupt Enable for the RTC Input Capture Channel 4 14 1 read-write IC4LH Polarity of the Active-going Capture Edge for the Input Capture Channel 4 9 1 read-write ICOWUSEN Enable Overwrite of Unread Snapshots for All Input Capture Channels 15 1 read-write CR3SS RTC Control 3 for Configuring SensorStrobe Channel 0x50 16 read-write n 0x0 0xFFFFFFFF SS1EN Enable for SensorStrobe Channel 1 1 1 read-write SS1FEIRQEN Falling Edge Interrupt Enable for the SensorStrobe Channel 1 5 1 read-write SS1IRQEN Interrupt Enable for SensorStrobe Channel 1 9 1 read-write SS2EN Enable for the SensorStrobe Channel 2 2 1 read-write SS2FEIRQEN Falling Edge Interrupt Enable for the SensorStrobe Channel 2 6 1 read-write SS2IRQEN Posedge EdgeInterrupt Enable for the SensorStrobe Channel 2 10 1 read-write SS3EN Enable for the SensorStrobe Channel 3 3 1 read-write SS3FEIRQEN Falling Edge Interrupt Enable for the SensorStrobe Channel 3 7 1 read-write SS3IRQEN Posedge EdgeInterrupt Enable for the SensorStrobe Channel 3 11 1 read-write SS4EN Enable for the SensorStrobe Channel 4 4 1 read-write SS4FEIRQEN Falling Edge Interrupt Enable for the SensorStrobe Channel 4 8 1 read-write SS4IRQEN Posedge EdgeInterrupt Enable for the SensorStrobe Channel 4 12 1 read-write CR4SS RTC Control 4 for Configuring SensorStrobe Channel 0x54 16 read-write n 0x0 0xFFFFFFFF SS1ARLEN Enable for Fine Control on SensorStrobe Channel 1 Period and Duty Cycle 9 1 read-write SS1MSKEN Enable for Thermometer-Code Masking of the SensorStrobe Channel 1 1 1 read-write NO_MSK Do not apply a mask to SensorStrobe Channel 1 Register 0 THERM_MSK Apply thermometer decoded mask 1 SS1POL SensorSTrobe Channel 1 Polarity Control 5 1 read-write SS2ARLEN Enable for Fine Control on SensorStrobe Channel 2 Period and Duty Cycle 10 1 read-write SS2MSKEN Enable for Thermometer-Code Masking of the SensorStrobe Channel 2 2 1 read-write SS2POL SensorStrobe Channel 2 Polarity Control 6 1 read-write SS3ARLEN Enable for Fine Control on SensorStrobe Channel 3 Period and Duty Cycle 11 1 read-write SS3MSKEN Enable for Thermometer-Code Masking of the SensorStrobe Channel 3 3 1 read-write SS3POL SensorStrobe Channel 3 Polarity Control 7 1 read-write SS4MSKEN Enable for Thermometer-Code Masking of the SensorStrobe Channel 4 4 1 read-write SS4POL SensorStrobe Channel 4 Polarity Control 8 1 read-write CR5SSS RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling 0xC4 16 read-write n 0x0 0xFFFFFFFF SS1SMPEN GPIO Input Sample Enable for SensorStrobe Channel 1 0 3 read-write SS1SMPMTCHIRQEN Sample Activity Interrupt Enable for SensorStrobe Channel 1 3 1 read-write SS2SMPEN GPIO Input Sample Enable for SensorStrobe Channel 2 4 3 read-write SS2SMPMTCHIRQEN Sample Activity Interrupt Enable for SensorStrobe Channel 2 7 1 read-write SS3SMPEN GPIO Input Sample Enable for SensorStrobe Channel 3 8 3 read-write SS3SMPMTCHIRQEN Sample Activity Interrupt Enable for SensorStrobe Channel 3 11 1 read-write CR6SSS RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge 0xC8 16 read-write n 0x0 0xFFFFFFFF SS1SMPONFE GPIO Sample Around Falling Edge of SensorStrobe Channel 1 0 2 read-write SS1NOFES No sampling of input around falling edge 0 SS1BFES Input sampled one clock cycle before falling edge of the SensorStrobe channel 1 1 SS1FES Input sampled at falling edge of the SensorStrobe channel 1 2 SS1AFES Input sampled one clock cycle after falling edge of the SensorStrobe channel 1 3 SS1SMPONRE GPIO Sample Around Rising Edge of SensorStrobe Channel 1 2 2 read-write SS1NORES No sampling of input around rising edge 0 SS1BRES Input sampled one clock cycle before rising edge of the SensorStrobe channel 1 1 SS1RES Input sampled at rising edge of the SensorStrobe channel 1 2 SS1ARES Input sampled one clock cycle after rising edge of the SensorStrobe channel 1 3 SS2SMPONFE GPIO Sample Around Falling Edge of SensorStrobe Channel 2 4 2 read-write SS2NOFES No sampling of input around falling edge 0 SS2BFES Input sampled one clock cycle before falling edge of the SensorStrobe channel 2 1 SS2FES Input sampled at falling edge of the SensorStrobe channel 2 2 SS2AFES Input sampled one clock cycle after falling edge of the SensorStrobe channel 2 3 SS2SMPONRE GPIO Sample Around Rising Edge of SensorStrobe Channel 2 6 2 read-write SS2NORES No sampling of input around rising edge 0 SS2BRES Input sampled one clock cycle before rising edge of the SensorStrobe channel 2 1 SS2RES Input sampled at rising edge of the SensorStrobe channel 2 2 SS2ARES Input sampled one clock cycle after rising edge of the SensorStrobe channel 2 3 SS3SMPONFE GPIO Sample Around Falling Edge of SensorStrobe Channel 3 8 2 read-write SS3NOFES No sampling of input around falling edge 0 SS3BFES Input sampled one clock cycle before falling edge of the SensorStrobe channel 3 1 SS3FES Input sampled at falling edge of the SensorStrobe channel 3 2 SS3AFES Input sampled one clock cycle after falling edge of the SensorStrobe channel 3 3 SS3SMPONRE GPIO Sample Around Rising Edge of SensorStrobe Channel 3 10 2 read-write SS3NORES No sampling of input around rising edge 0 SS3BRES Input sampled one clock cycle before rising edge of the SensorStrobe channel 3 1 SS3RES Input sampled at rising edge of the SensorStrobe channel 3 2 SS3ARES Input sampled one clock cycle after rising edge of the SensorStrobe channel 3 3 CR7SSS RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity 0xCC 16 read-write n 0x0 0xFFFFFFFF SS1SMPEXP Expected GPIO Sample for SensorStrobe Channel 1 0 3 read-write SS1SMPPTRN Sample Activity Selection for SensorStrobe Channel 1 3 2 read-write SS1SMPCHNG Current GPIO sample is not same as previous sample 0 SS1SMPSAME Current GPIO sample is same as previous sample 1 SS1SMPMTCH Current GPIO sample is same as expected sample 2 SS1SMPNOMTCH Current GPIO sample is not same as expected sample 3 SS2SMPEXP Expected GPIO Sample for SensorStrobe Channel 2 5 3 read-write SS2SMPPTRN Sample Activity Selection for SensorStrobe Channel 2 8 2 read-write SS2SMPCHNG Current GPIO sample is not same as previous sample 0 SS2SMPSAME Current GPIO sample is same as previous sample 1 SS2SMPMTCH Current GPIO sample is same as expected sample 2 SS2SMPNOMTCH Current GPIO sample is not same as expected sample 3 SS3SMPEXP Expected GPIO Sample for SensorStrobe Channel 3 10 3 read-write SS3SMPPTRN Sample Activity Selection for SensorStrobe Channel 3 13 2 read-write SS3SMPCHNG Current GPIO sample is not same as previous sample 0 SS3SMPSAME Current GPIO sample is same as previous sample 1 SS3SMPMTCH Current GPIO sample is same as expected sample 2 SS3SMPNOMTCH Current GPIO sample is not same as expected sample 3 FRZCNT RTC Freeze Count 0x90 16 read-write n 0x0 0xFFFFFFFF FRZCNT RTC Freeze Count. Coherent, Triple 16-Bit Read of the 47-Bit RTC Count 0 16 read-only GPMUX0 RTC GPIO Pin Mux Control Register 0 0xE0 16 read-write n 0x4688 0xFFFFFFFF SS1GPIN0SEL GPIO Mux Selection for SensorStrobe Channel 1 Input0 0 3 read-write SS1GPIN1SEL GPIO Mux Selection for SensorStrobe Channel 1 Input 1 3 3 read-write SS1GPIN2SEL GPIO Mux Selection for SensorStrobe Channel 1 Input 2 6 3 read-write SS2GPIN0SEL GPIO Mux Selection for SensorStrobe Channel 2 Input 0 9 3 read-write SS2GPIN1SEL GPIO Mux Selection for SensorStrobe Channel 2 Input 1 12 3 read-write GPMUX1 RTC GPIO Pin Mux Control Register 1 0xE4 16 read-write n 0x1F5 0xFFFFFFFF SS1DIFFOUT Differential SensorStrobe Out Option for SensorStrobe Channel 1 14 1 read-write SS2GPIN2SEL GPIO Mux Selection for SensorStrobe Channel 2 Input 2 0 3 read-write SS3DIFFOUT Differential SensorStrobe Out Option for SensorStrobe Channel 3 15 1 read-write SS3GPIN0SEL GPIO Mux Selection for SensorStrobe Channel 3 Input 0 3 3 read-write SS3GPIN1SEL GPIO Mux Selection for SensorStrobe Channel 3 Input 1 6 3 read-write SS3GPIN2SEL GPIO Mux Selection for SensorStrobe Channel 3 Input 2 9 3 read-write GWY RTC Gateway 0x20 16 read-write n 0x0 0xFFFFFFFF SWKEY Software-keyed Command Issued by the CPU 0 16 write-only IC2 RTC Input Capture Channel 2 0x64 16 read-write n 0x0 0xFFFFFFFF IC2 RTC Input Capture Channel 2 0 16 read-only IC3 RTC Input Capture Channel 3 0x68 16 read-write n 0x0 0xFFFFFFFF IC3 RTC Input Capture Channel 3 0 16 read-only IC4 RTC Input Capture Channel 4 0x6C 16 read-write n 0x0 0xFFFFFFFF IC4 RTC Input Capture Channel 4 0 16 read-only MOD RTC Modulo 0x3C 16 read-write n 0x40 0xFFFFFFFF CNT0_4TOZERO Mirror of CNT0[4:0] 11 5 read-only CNTMOD60 Modulo-60 Value of the RTC Count: CNT1 and CNT0 0 6 read-only INCR Most Recent Increment Value Added to the RTC Count in CNT1 and CNT0 6 4 read-only TRMBDY Trim Boundary Indicator 10 1 read-only SNAP0 RTC Snapshot 0 0x30 16 read-write n 0x0 0xFFFFFFFF VALUE Constituent Part of the 47-bit Input Capture Channel 0, Containing a Sticky Snapshot of CNT0 0 16 read-only SNAP1 RTC Snapshot 1 0x34 16 read-write n 0x0 0xFFFFFFFF VALUE Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT1 0 16 read-only SNAP2 RTC Snapshot 2 0x38 16 read-write n 0x0 0xFFFFFFFF VALUE Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT2 0 15 read-only SR0 RTC Status 0 0x4 16 read-write n 0x3F80 0xFFFFFFFF ALMINT Alarm Interrupt Source 1 1 read-write ISOENB Visibility of 32kHz Sourced Registers 14 1 read-only ISOINT RTC Power-Domain Isolation Interrupt Source 3 1 read-write MOD60ALMINT Modulo-60 RTC Alarm Interrupt Source 2 1 read-write WPNDERRINT Write Pending Error Interrupt Source 4 1 read-write WPNDINT Write Pending Interrupt 6 1 read-write WSYNCALM0 Synchronisation Status of Posted Writes to ALM0 11 1 read-only WSYNCALM1 Synchronisation Status of Posted Writes to ALM1 12 1 read-only WSYNCCNT0 Synchronisation Status of Posted Writes to CNT0 9 1 read-only WSYNCCNT1 Synchronisation Status of Posted Writes to CNT1 10 1 read-only WSYNCCR0 Synchronisation Status of Posted Writes to CR0 7 1 read-only WSYNCINT Write Synchronisation Interrupt 5 1 read-write WSYNCSR0 Synchronisation Status of Posted Writes to SR0 8 1 read-only WSYNCTRM Synchronisation Status of Posted Writes to TRM 13 1 read-only SR1 RTC Status 1 0x8 16 read-write n 0x78 0xFFFFFFFF WPNDALM0 Pending Status of Posted Writes to ALM0 11 1 read-only WPNDALM1 Pending Status of Posted Writes to ALM1 12 1 read-only WPNDCNT0 Pending Status of Posted Writes to CNT0 9 1 read-only WPNDCNT1 Pending Status of Posted Writes to CNT1 10 1 read-only WPNDCR0 Pending Status of Posted Writes to CR0 7 1 read-only WPNDSR0 Pending Status of Posted Clearances of Interrupt Sources in SR0 8 1 read-only WPNDTRM Pending Status of Posted Writes to TRM 13 1 read-only SR2 RTC Status 2 0x2C 16 read-write n 0xC000 0xFFFFFFFF CNTINT RTC Count Interrupt Source 0 1 read-write CNTMOD60ROLL RTC Count Modulo-60 Roll-Over 6 1 read-only CNTMOD60ROLLINT RTC Modulo-60 Count Roll-Over Interrupt Source 4 1 read-write CNTROLL RTC Count Roll-Over 5 1 read-only CNTROLLINT RTC Count Roll-Over Interrupt Source 3 1 read-write PSINT RTC Prescaled, Modulo-1 Boundary Interrupt Source 1 1 read-write TRMBDYMIR Mirror of MOD:RTCTRMBDY 7 1 read-only TRMINT RTC Trim Interrupt Source 2 1 read-write WPNDALM2MIR Pending Status of Posted Writes to ALM2 13 1 read-only WPNDCR1MIR Pending Status of Posted Writes to CR1 12 1 read-only WSYNCALM2MIR Synchronization Status of Posted Writes to ALM2 15 1 read-only WSYNCCR1MIR Synchronization Status of Posted Writes to CR1 14 1 read-only SR3 RTC Status 3 0x48 16 read-write n 0x0 0xFFFFFFFF ALMINTMIR Read-only Mirror of the SR0:ALMINT Interrupt Source 13 1 read-only IC0IRQ Sticky Interrupt Source for the RTC Input Capture Channel 0 0 1 read-write IC2IRQ Sticky Interrupt Source for the RTC Input Capture Channel 2 2 1 read-write IC3IRQ Sticky Interrupt Source for the RTC Input Capture Channel 3 3 1 read-write IC4IRQ Sticky Interrupt Source for the RTC Input Capture Channel 4 4 1 read-write SS1FEIRQ Sticky Interrupt Source for the SensorStrobe Channel 1 Falling Edge 5 1 read-write SS1IRQ Sticky Interrupt Source for SensorStrobe Channel 1 9 1 read-write SS2FEIRQ Sticky Interrupt Source for the SensorStrobe Channel 2 Falling Edge 6 1 read-write SS2IRQ Sticky Interrupt Source for the SensorStrobe Channel 2 10 1 read-write SS3FEIRQ Sticky Interrupt Source for the SensorStrobe Channel 3 Falling Edge 7 1 read-write SS3IRQ Sticky Interrupt Source for the SensorStrobe Channel 3 11 1 read-write SS4FEIRQ Sticky Interrupt Source for the SensorStrobe Channel 4 Falling Edge 8 1 read-write SS4IRQ Sticky Interrupt Source for the SensorStrobe Channel 4 12 1 read-write SR4 RTC Status 4 0x80 16 read-write n 0xF7DF 0xFFFFFFFF RSYNCIC0 Synchronization Status of Posted Reads of RTC Input Channel 0 10 1 read-only RSYNCIC2 Synchronization Status of Posted Reads of RTC Input Channel 2 12 1 read-only RSYNCIC3 Synchronization Status of Posted Reads of RTC Input Channel 3 13 1 read-only RSYNCIC4 Synchronization Status of Posted Reads of RTC Input Channel 4 14 1 read-only WSYNCCR2IC Synchronization Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register 1 1 read-only WSYNCCR3SS Synchronization Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register 2 1 read-only WSYNCCR4SS Synchronization Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register 3 1 read-only WSYNCSR3 Synchronisation Status of Posted Writes to SR3 0 1 read-only WSYNCSS1 Synchronization Status of Posted Writes to SensorStrobe Channel 1 6 1 read-only WSYNCSS2 Synchronization Status of Posted Writes to SensorStrobe Channel 2 7 1 read-only WSYNCSS3 Synchronization Status of Posted Writes to SensorStrobe Channel 3 8 1 read-only WSYNCSS4 Synchronization Status of Posted Writes to SensorStrobe Channel 4 9 1 read-only WSYNCSSMSK Synchronization Status of Posted Writes to Masks for SensorStrobe Channel Register 4 1 read-only WSYNCSSMSKOT Synchronization Status of Posted Reads Writes to Mask for SensorStrobe Channels on Time Control Register 15 1 read-only SR5 RTC Status 5 0x84 16 read-write n 0x0 0xFFFFFFFF RPENDIC0 Pending Status of Posted Reads of Input Capture Channel 0 10 1 read-only RPENDIC2 Pending Status of Posted Reads of IC2 12 1 read-only RPENDIC3 Pending Status of Posted Reads of IC3 13 1 read-only RPENDIC4 Pending Status of Posted Reads of IC4 14 1 read-only WPENDCR2IC Pending Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register 1 1 read-only WPENDCR3SS Pending Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register 2 1 read-only WPENDCR4SS Pending Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register 3 1 read-only WPENDSR3 Pending Status of Posted Clearances of Interrupt Sources in RTC Status 3 Register 0 1 read-only WPENDSS1 Pending Status of Posted Writes to SensorStrobe Channel 1 6 1 read-only WPENDSS2 Pending Status of Posted Writes to SensorStrobe Channel 2 7 1 read-only WPENDSS3 Pending Status of Posted Writes to SensorStrobe Channel 3 8 1 read-only WPENDSS4 Pending Status of Posted Writes to SensorStrobe Channel 4 9 1 read-only WPENDSSMSK Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register 4 1 read-only WPENDSSMSKOT Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register 15 1 read-only SR6 RTC Status 6 0x88 16 read-write n 0x7900 0xFFFFFFFF FRZCNTPTR Pointer for the Triple-Read Sequence of FRZCNT 9 2 read-only IC0SNAP Confirmation That RTC Snapshot 0, 1, 2 Registers Reflect the Value of Input-Capture Channel RTC Input Capture Channel 0 8 1 read-only IC0UNR Sticky Unread Status of the Input Capture Channel 0 0 1 read-only IC2UNR Sticky Unread Status of the Input Capture Channel 2 2 1 read-only IC3UNR Sticky Unread Status of the Input Capture Channel 3 3 1 read-only IC4UNR Sticky Unread Status of the Input Capture Channel 4 4 1 read-only SR7 RTC Status 7 0xD0 16 read-write n 0x0 0xFFFFFFFF SS1OUT Output Value for SensorStrobe Channel 1 12 1 read-only SS1SMP Latest GPIO Sample for SensorStrobe Channel 1 0 3 read-only SS1SMPMTCHIRQ Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 1 3 1 read-write SS2OUT Output Value for SensorStrobe Channel 2 13 1 read-only SS2SMP Latest GPIO Sample for SensorStrobe Channel 2 4 3 read-only SS2SMPMTCHIRQ Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 2 7 1 read-write SS3OUT Output Value for SensorStrobe Channel 3 14 1 read-only SS3SMP Latest GPIO Sample for SensorStrobe Channel 3 8 3 read-only SS3SMPMTCHIRQ Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 3 11 1 read-write SS4OUT Output Value for SensorStrobe Channel 4 15 1 read-only SR8 RTC Status 8 0xD4 16 read-write n 0x3F77 0xFFFFFFFF WSYNCCR5SSS Synchronisation Status of Posted Writes to Control 5 for Configuring SensorStrobe Channel Register 8 1 read-only WSYNCCR6SSS Synchronisation Status of Posted Writes to Control 6 for Configuring SensorStrobe Channel Register 9 1 read-only WSYNCCR7SSS Synchronisation Status of Posted Writes to Control 7 for Configuring SensorStrobe Channel Register 10 1 read-only WSYNCGPMUX0 Synchronisation Status of Posted Writes to GPIO Pin Mux Control Register 0 12 1 read-only WSYNCGPMUX1 Synchronisation Status of Posted Writes to GPIO Pin Mux Control Register 1 13 1 read-only WSYNCSR7 Synchronisation Status of Posted Writes to Status 7 Register 11 1 read-only WSYNCSS1HIGHDUR Synchronisation Status of Posted Writes to SensorStrobe Channel 1 High Duration Register 4 1 read-only WSYNCSS1LOWDUR Synchronisation Status of Posted Writes to SensorStrobe Channel 1 Low Duration Register 0 1 read-only WSYNCSS2HIGHDUR Synchronisation Status of Posted Writes to SensorStrobe Channel 2 High Duration Register 5 1 read-only WSYNCSS2LOWDUR Synchronisation Status of Posted Writes to SensorStrobe Channel 2 Low Duration Register 1 1 read-only WSYNCSS3HIGHDUR Synchronisation Status of Posted Writes to SensorStrobe Channel 3 High Duration Register 6 1 read-only WSYNCSS3LOWDUR Synchronisation Status of Posted Writes to SensorStrobe Channel 3 Low Duration Register 2 1 read-only SR9 RTC Status 9 0xD8 16 read-write n 0x0 0xFFFFFFFF WPENDCR5SSS Pending Status of Posted Writes to Control 5 for Configuring SensorStrobe Channel Register 8 1 read-only WPENDCR6SSS Pending Status of Posted Writes to Control 6 for Configuring SensorStrobe Channel Register 9 1 read-only WPENDCR7SSS Pending Status of Posted Writes to Control 7 for Configuring SensorStrobe Channel Register 10 1 read-only WPENDGPMUX0 Pending Status of Posted Writes to GPMUX0 12 1 read-only WPENDGPMUX1 Pending Status of Posted Writes to GPMUX1 13 1 read-only WPENDSR7 Pending Status of Posted Writes to SR7 11 1 read-only WPENDSS1HIGHDUR Pending Status of Posted Writes to SensortStrobe Channel 1 High Duration Register 4 1 read-only WPENDSS1LOWDUR Pending Status of Posted Writes to SensortStrobe Channel 1 Low Duration Register 0 1 read-only WPENDSS2HIGHDUR Pending Status of Posted Writes to SensortStrobe Channel 2 High Duration Register 5 1 read-only WPENDSS2LOWDUR Pending Status of Posted Writes to SensortStrobe Channel 2 Low Duration Register 1 1 read-only WPENDSS3HIGHDUR Pending Status of Posted Writes to SensortStrobe Channel 3 High Duration Register 6 1 read-only WPENDSS3LOWDUR Pending Status of Posted Writes to SensortStrobe Channel 3 Low Duration Register 2 1 read-only SS1 RTC SensorStrobe Channel 1 0x70 16 read-write n 0x8000 0xFFFFFFFF SS1 SensorStrobe Channel 1 0 16 read-write SS1HIGHDUR RTC Auto-Reload High Duration for SensorStrobe Channel 1 0xB0 16 read-write n 0x8000 0xFFFFFFFF SS1HIGHDUR High Duration for SensorStrobe Channel 1 0 16 read-write SS1LOWDUR RTC Auto-Reload Low Duration for SensorStrobe Channel 1 0xA0 16 read-write n 0x8000 0xFFFFFFFF SS1LOWDUR Low Duration for SensorStrobe Channel 1 0 16 read-write SS1TGT RTC SensorStrobe Channel 1 Target 0x8C 16 read-write n 0x8000 0xFFFFFFFF SS1TGT Current Target Value for the SensorStrobe Channel 1 0 16 read-only SS2 RTC SensorStrobe Channel 2 0x74 16 read-write n 0x8000 0xFFFFFFFF SS2 SensorStrobe Channel 2 0 16 read-write SS2HIGHDUR RTC Auto-Reload High Duration for SensorStrobe Channel 2 0xB4 16 read-write n 0x8000 0xFFFFFFFF SS2HIGHDUR High Duration for SensorStrobe Channel 2 0 16 read-write SS2LOWDUR RTC Auto-Reload Low Duration for SensorStrobe Channel 2 0xA4 16 read-write n 0x8000 0xFFFFFFFF SS2LOWDUR Low Duration for SensorStrobe Channel 2 0 16 read-write SS2TGT RTC SensorStrobe Channel 2 Target 0x94 16 read-write n 0x8000 0xFFFFFFFF SS2TGT Current, Cumulative Target Time for SensorStrobe Channel 2, Taking Account of Any Auto-reloading 0 16 read-only SS3 RTC SensorStrobe Channel 3 0x78 16 read-write n 0x8000 0xFFFFFFFF SS3 SensorStrobe Channel 3 0 16 read-write SS3HIGHDUR RTC Auto-Reload High Duration for SensorStrobe Channel 3 0xB8 16 read-write n 0x8000 0xFFFFFFFF SS3HIGHDUR High Duration for SensorStrobe Channel 3 0 16 read-write SS3LOWDUR RTC Auto-Reload Low Duration for SensorStrobe Channel 3 0xA8 16 read-write n 0x8000 0xFFFFFFFF SS3LOWDUR Low Duration for SensorStrobe Channel 3 0 16 read-write SS3TGT RTC SensorStrobe Channel 3 Target 0x98 16 read-write n 0x8000 0xFFFFFFFF SS3TGT Current, Cumulative Target Time for SensorStrobe Channel 3, Taking Account of Any Auto-reloading 0 16 read-only SS4 RTC SensorStrobe Channel 4 0x7C 16 read-write n 0x8000 0xFFFFFFFF SS4 SensorStrobe Channel 4 0 16 read-write SSMSK RTC Mask for SensorStrobe Channel 0x58 16 read-write n 0x0 0xFFFFFFFF SS1MSK Concatenation of Thermometer-Encoded Masks for the 16-bit SensorStrobe Channels 0 4 read-write SS2MSK SensorStrobe Channel 2 Period Control 4 4 read-write SS3MSK SensorStrobe Channel 3 Period Control 8 4 read-write SS4MSK SensorStrobe Channel 4 Period Control 12 4 read-write SSMSKOT RTC Masks for SensorStrobe Channels on Time Control 0xC0 16 read-write n 0x0 0xFFFFFFFF SS1MSKOT Concatenation of Thermometer-encoded Masks for the 16-bit SensorStrobe Channels 0 4 read-write SS2MSKOT SensorStrobe Channel 2 on Time Control 4 4 read-write SS3MSKOT SensorStrobe Channel 3 on Time Control 8 4 read-write SS4MSKOT SensorStrobe Channel 4 on Time Control 12 4 read-write TRM RTC Trim 0x1C 16 read-write n 0x398 0xFFFFFFFF ADD Trim Polarity 3 1 read-write IVL Trim Interval in Prescaled RTC Time Units 4 2 read-write IVL2EXPMIN Minimum Power-of-two Interval of Prescaled RTC Time Units Which TRM:TRMIVL TRMIVL Can Select 6 4 read-write VALUE Trim Value in Prescaled RTC Time Units to Be Added or Subtracted from the RTC Count at the End of a Periodic Interval Selected by TRM:TRMIVL 0 3 read-write SPI0 Serial Peripheral Interface SPI0 0x40004000 0x0 0x100 registers n SPI0_EVT Event 15 CNT Transfer Byte Count 0x18 16 read-write n 0x0 0xFFFFFFFF FRAMECONT Continue Frame 15 1 read-write VALUE Transfer Byte Count 0 14 read-write CS_CTL Chip Select Control for Multi-slave Connections 0x30 16 read-write n 0x1 0xFFFFFFFF SEL Chip Select Control 0 4 read-write CS_OVERRIDE Chip Select Override 0x34 16 read-write n 0x0 0xFFFFFFFF CTL CS Override Control 0 2 read-write CTL SPI Configuration 0x10 16 read-write n 0x0 0xFFFFFFFF CON Continuous Transfer Enable 11 1 read-write CPHA Serial Clock Phase Mode 2 1 read-write CPOL Serial Clock Polarity 3 1 read-write CSRST Reset Mode for CS Error Bit 14 1 read-write LOOPBACK Loopback Enable 10 1 read-write LSB LSB First Transfer Enable 5 1 read-write MASEN Master Mode Enable 1 1 read-write OEN Slave MISO Output Enable 9 1 read-write RFLUSH SPI Rx FIFO Flush Enable 12 1 read-write RXOF Rx Overflow Overwrite Enable 8 1 read-write SPIEN SPI Enable 0 1 read-write TFLUSH SPI Tx FIFO Flush Enable 13 1 read-write TIM SPI Transfer and Interrupt Mode 6 1 read-write WOM SPI Wired-OR Mode 4 1 read-write ZEN Transmit Zeros Enable 7 1 read-write DIV SPI Baud Rate Selection 0xC 16 read-write n 0x0 0xFFFFFFFF VALUE SPI Clock Divider 0 6 read-write DMA SPI DMA Enable 0x1C 16 read-write n 0x0 0xFFFFFFFF EN Enable DMA for Data Transfer 0 1 read-write RXEN Enable Receive DMA Request 2 1 read-write TXEN Enable Transmit DMA Request 1 1 read-write FIFO_STAT FIFO Status 0x20 16 read-write n 0x0 0xFFFFFFFF RX SPI Rx FIFO Status 8 4 read-only TX SPI Tx FIFO Status 0 4 read-only FLOW_CTL Flow Control 0x28 16 read-write n 0x0 0xFFFFFFFF MODE Flow Control Mode 0 2 read-write RDBURSTSZ Read Data Burst Size - 1 6 10 read-write RDYPOL Polarity of RDY/MISO Line 4 1 read-write IEN SPI Interrupts Enable 0x14 16 read-write n 0x0 0xFFFFFFFF CS Enable Interrupt on Every CS Edge in Slave CON Mode 8 1 read-write IRQMODE SPI IRQ Mode Bits 0 3 read-write RDY Ready Signal Edge Interrupt Enable 11 1 read-write RXOVR Rx Overflow Interrupt Enable 10 1 read-write TXDONE SPI Transmit Done Interrupt Enable 12 1 read-write TXEMPTY Tx FIFO Empty Interrupt Enable 14 1 read-write TXUNDR Tx Underflow Interrupt Enable 9 1 read-write XFRDONE SPI Transfer Completion Interrupt Enable 13 1 read-write RD_CTL Read Control 0x24 16 read-write n 0x0 0xFFFFFFFF CMDEN Read Command Enable 0 1 read-write OVERLAP Tx/Rx Overlap Mode 1 1 read-write THREEPIN Three Pin SPI Mode 8 1 read-write TXBYTES Transmit Byte Count - 1 (Read Command) 2 4 read-write RX Receive 0x4 16 read-write n 0x0 0xFFFFFFFF BYTE1 8-bit Receive Buffer 0 8 read-only BYTE2 8-bit Receive Buffer, Used Only in DMA Modes 8 8 read-only STAT Status 0x0 16 read-write n 0x800 0xFFFFFFFF CS CS Status 11 1 read-only CSERR Detected a CS Error Condition in Slave Mode 12 1 read-only CSFALL Detected a Falling Edge on CS, in Slave CON Mode 14 1 read-only CSRISE Detected a Rising Edge on CS, in Slave CON Mode 13 1 read-only IRQ SPI Interrupt Status 0 1 read-only RDY Detected an Edge on Ready Indicator for Flow Control 15 1 read-only RXIRQ SPI Rx IRQ 6 1 read-only RXOVR SPI Rx FIFO Overflow 7 1 read-only TXDONE SPI Tx Done in Read Command Mode 3 1 read-only TXEMPTY SPI Tx FIFO Empty Interrupt 2 1 read-only TXIRQ SPI Tx IRQ 5 1 read-only TXUNDR SPI Tx FIFO Underflow 4 1 read-only XFRDONE SPI Transfer Completion 1 1 read-only TX Transmit 0x8 16 read-write n 0x0 0xFFFFFFFF BYTE1 8-bit Transmit Buffer 0 8 write-only BYTE2 8-bit Transmit Buffer, Used Only in DMA Modes 8 8 write-only WAIT_TMR Wait Timer for Flow Control 0x2C 16 read-write n 0x0 0xFFFFFFFF VALUE Wait Timer 0 16 read-write SPI1 Serial Peripheral Interface SPI0 0x40004400 0x0 0x100 registers n SPI1_EVT Event 42 CNT Transfer Byte Count 0x18 16 read-write n 0x0 0xFFFFFFFF FRAMECONT Continue Frame 15 1 read-write VALUE Transfer Byte Count 0 14 read-write CS_CTL Chip Select Control for Multi-slave Connections 0x30 16 read-write n 0x1 0xFFFFFFFF SEL Chip Select Control 0 4 read-write CS_OVERRIDE Chip Select Override 0x34 16 read-write n 0x0 0xFFFFFFFF CTL CS Override Control 0 2 read-write CTL SPI Configuration 0x10 16 read-write n 0x0 0xFFFFFFFF CON Continuous Transfer Enable 11 1 read-write CPHA Serial Clock Phase Mode 2 1 read-write CPOL Serial Clock Polarity 3 1 read-write CSRST Reset Mode for CS Error Bit 14 1 read-write LOOPBACK Loopback Enable 10 1 read-write LSB LSB First Transfer Enable 5 1 read-write MASEN Master Mode Enable 1 1 read-write OEN Slave MISO Output Enable 9 1 read-write RFLUSH SPI Rx FIFO Flush Enable 12 1 read-write RXOF Rx Overflow Overwrite Enable 8 1 read-write SPIEN SPI Enable 0 1 read-write TFLUSH SPI Tx FIFO Flush Enable 13 1 read-write TIM SPI Transfer and Interrupt Mode 6 1 read-write WOM SPI Wired-OR Mode 4 1 read-write ZEN Transmit Zeros Enable 7 1 read-write DIV SPI Baud Rate Selection 0xC 16 read-write n 0x0 0xFFFFFFFF VALUE SPI Clock Divider 0 6 read-write DMA SPI DMA Enable 0x1C 16 read-write n 0x0 0xFFFFFFFF EN Enable DMA for Data Transfer 0 1 read-write RXEN Enable Receive DMA Request 2 1 read-write TXEN Enable Transmit DMA Request 1 1 read-write FIFO_STAT FIFO Status 0x20 16 read-write n 0x0 0xFFFFFFFF RX SPI Rx FIFO Status 8 4 read-only TX SPI Tx FIFO Status 0 4 read-only FLOW_CTL Flow Control 0x28 16 read-write n 0x0 0xFFFFFFFF MODE Flow Control Mode 0 2 read-write RDBURSTSZ Read Data Burst Size - 1 6 10 read-write RDYPOL Polarity of RDY/MISO Line 4 1 read-write IEN SPI Interrupts Enable 0x14 16 read-write n 0x0 0xFFFFFFFF CS Enable Interrupt on Every CS Edge in Slave CON Mode 8 1 read-write IRQMODE SPI IRQ Mode Bits 0 3 read-write RDY Ready Signal Edge Interrupt Enable 11 1 read-write RXOVR Rx Overflow Interrupt Enable 10 1 read-write TXDONE SPI Transmit Done Interrupt Enable 12 1 read-write TXEMPTY Tx FIFO Empty Interrupt Enable 14 1 read-write TXUNDR Tx Underflow Interrupt Enable 9 1 read-write XFRDONE SPI Transfer Completion Interrupt Enable 13 1 read-write RD_CTL Read Control 0x24 16 read-write n 0x0 0xFFFFFFFF CMDEN Read Command Enable 0 1 read-write OVERLAP Tx/Rx Overlap Mode 1 1 read-write THREEPIN Three Pin SPI Mode 8 1 read-write TXBYTES Transmit Byte Count - 1 (Read Command) 2 4 read-write RX Receive 0x4 16 read-write n 0x0 0xFFFFFFFF BYTE1 8-bit Receive Buffer 0 8 read-only BYTE2 8-bit Receive Buffer, Used Only in DMA Modes 8 8 read-only STAT Status 0x0 16 read-write n 0x800 0xFFFFFFFF CS CS Status 11 1 read-only CSERR Detected a CS Error Condition in Slave Mode 12 1 read-only CSFALL Detected a Falling Edge on CS, in Slave CON Mode 14 1 read-only CSRISE Detected a Rising Edge on CS, in Slave CON Mode 13 1 read-only IRQ SPI Interrupt Status 0 1 read-only RDY Detected an Edge on Ready Indicator for Flow Control 15 1 read-only RXIRQ SPI Rx IRQ 6 1 read-only RXOVR SPI Rx FIFO Overflow 7 1 read-only TXDONE SPI Tx Done in Read Command Mode 3 1 read-only TXEMPTY SPI Tx FIFO Empty Interrupt 2 1 read-only TXIRQ SPI Tx IRQ 5 1 read-only TXUNDR SPI Tx FIFO Underflow 4 1 read-only XFRDONE SPI Transfer Completion 1 1 read-only TX Transmit 0x8 16 read-write n 0x0 0xFFFFFFFF BYTE1 8-bit Transmit Buffer 0 8 write-only BYTE2 8-bit Transmit Buffer, Used Only in DMA Modes 8 8 write-only WAIT_TMR Wait Timer for Flow Control 0x2C 16 read-write n 0x0 0xFFFFFFFF VALUE Wait Timer 0 16 read-write SPI2 Serial Peripheral Interface SPI0 0x40024000 0x0 0x100 registers n SPI2_EVT Event 16 CNT Transfer Byte Count 0x18 16 read-write n 0x0 0xFFFFFFFF FRAMECONT Continue Frame 15 1 read-write VALUE Transfer Byte Count 0 14 read-write CS_CTL Chip Select Control for Multi-slave Connections 0x30 16 read-write n 0x1 0xFFFFFFFF SEL Chip Select Control 0 4 read-write CS_OVERRIDE Chip Select Override 0x34 16 read-write n 0x0 0xFFFFFFFF CTL CS Override Control 0 2 read-write CTL SPI Configuration 0x10 16 read-write n 0x0 0xFFFFFFFF CON Continuous Transfer Enable 11 1 read-write CPHA Serial Clock Phase Mode 2 1 read-write CPOL Serial Clock Polarity 3 1 read-write CSRST Reset Mode for CS Error Bit 14 1 read-write LOOPBACK Loopback Enable 10 1 read-write LSB LSB First Transfer Enable 5 1 read-write MASEN Master Mode Enable 1 1 read-write OEN Slave MISO Output Enable 9 1 read-write RFLUSH SPI Rx FIFO Flush Enable 12 1 read-write RXOF Rx Overflow Overwrite Enable 8 1 read-write SPIEN SPI Enable 0 1 read-write TFLUSH SPI Tx FIFO Flush Enable 13 1 read-write TIM SPI Transfer and Interrupt Mode 6 1 read-write WOM SPI Wired-OR Mode 4 1 read-write ZEN Transmit Zeros Enable 7 1 read-write DIV SPI Baud Rate Selection 0xC 16 read-write n 0x0 0xFFFFFFFF VALUE SPI Clock Divider 0 6 read-write DMA SPI DMA Enable 0x1C 16 read-write n 0x0 0xFFFFFFFF EN Enable DMA for Data Transfer 0 1 read-write RXEN Enable Receive DMA Request 2 1 read-write TXEN Enable Transmit DMA Request 1 1 read-write FIFO_STAT FIFO Status 0x20 16 read-write n 0x0 0xFFFFFFFF RX SPI Rx FIFO Status 8 4 read-only TX SPI Tx FIFO Status 0 4 read-only FLOW_CTL Flow Control 0x28 16 read-write n 0x0 0xFFFFFFFF MODE Flow Control Mode 0 2 read-write RDBURSTSZ Read Data Burst Size - 1 6 10 read-write RDYPOL Polarity of RDY/MISO Line 4 1 read-write IEN SPI Interrupts Enable 0x14 16 read-write n 0x0 0xFFFFFFFF CS Enable Interrupt on Every CS Edge in Slave CON Mode 8 1 read-write IRQMODE SPI IRQ Mode Bits 0 3 read-write RDY Ready Signal Edge Interrupt Enable 11 1 read-write RXOVR Rx Overflow Interrupt Enable 10 1 read-write TXDONE SPI Transmit Done Interrupt Enable 12 1 read-write TXEMPTY Tx FIFO Empty Interrupt Enable 14 1 read-write TXUNDR Tx Underflow Interrupt Enable 9 1 read-write XFRDONE SPI Transfer Completion Interrupt Enable 13 1 read-write RD_CTL Read Control 0x24 16 read-write n 0x0 0xFFFFFFFF CMDEN Read Command Enable 0 1 read-write OVERLAP Tx/Rx Overlap Mode 1 1 read-write THREEPIN Three Pin SPI Mode 8 1 read-write TXBYTES Transmit Byte Count - 1 (Read Command) 2 4 read-write RX Receive 0x4 16 read-write n 0x0 0xFFFFFFFF BYTE1 8-bit Receive Buffer 0 8 read-only BYTE2 8-bit Receive Buffer, Used Only in DMA Modes 8 8 read-only STAT Status 0x0 16 read-write n 0x800 0xFFFFFFFF CS CS Status 11 1 read-only CSERR Detected a CS Error Condition in Slave Mode 12 1 read-only CSFALL Detected a Falling Edge on CS, in Slave CON Mode 14 1 read-only CSRISE Detected a Rising Edge on CS, in Slave CON Mode 13 1 read-only IRQ SPI Interrupt Status 0 1 read-only RDY Detected an Edge on Ready Indicator for Flow Control 15 1 read-only RXIRQ SPI Rx IRQ 6 1 read-only RXOVR SPI Rx FIFO Overflow 7 1 read-only TXDONE SPI Tx Done in Read Command Mode 3 1 read-only TXEMPTY SPI Tx FIFO Empty Interrupt 2 1 read-only TXIRQ SPI Tx IRQ 5 1 read-only TXUNDR SPI Tx FIFO Underflow 4 1 read-only XFRDONE SPI Transfer Completion 1 1 read-only TX Transmit 0x8 16 read-write n 0x0 0xFFFFFFFF BYTE1 8-bit Transmit Buffer 0 8 write-only BYTE2 8-bit Transmit Buffer, Used Only in DMA Modes 8 8 write-only WAIT_TMR Wait Timer for Flow Control 0x2C 16 read-write n 0x0 0xFFFFFFFF VALUE Wait Timer 0 16 read-write SPORT0 Serial Port SPORT0 0x40038000 0x0 0x100 registers n SPORT_A_EVT Channel A Event 36 SPORT_B_EVT Channel B Event 37 CNVT_A Half SPORT 'A' CNV width 0x14 32 read-write n 0x0 0xFFFFFFFF CNVT2FS CNV to FS duration: Half SPORT A 16 8 read-write POL Polarity of the CNV signal 8 1 read-write WID CNV signal width: Half SPORT A 0 4 read-write CNVT_B Half SPORT 'B' CNV width register 0x54 32 read-write n 0x0 0xFFFFFFFF CNVT2FS CNV to FS duration: Half SPORT B 16 8 read-write POL Polarity of the CNV signal 8 1 read-write WID CNV signal width: Half SPORT B 0 4 read-write CTL_A Half SPORT 'A' Control Register 0x0 32 read-write n 0x0 0xFFFFFFFF CKMUXSEL Clock Multiplexer Select 2 1 read-write CTL_CLK_MUX_DIS Disable serial clock multiplexing 0 CTL_CLK_MUX_EN Enable serial clock multiplexing 1 CKRE Clock Rising Edge 12 1 read-write CTL_CLK_FALL_EDGE Clock falling edge 0 CTL_CLK_RISE_EDGE Clock rising edge 1 DATMUXSEL Data Multiplexer select 22 1 read-write DIFS Data-Independent Frame Sync 15 1 read-write CTL_DATA_DEP_FS Data-dependent frame sync 0 CTL_DATA_INDP_FS Data-independent frame sync 1 DMAEN DMA Enable 26 1 read-write FSERRMODE Frame Sync Error Operation 20 1 read-write FSMUXSEL Frame Sync Multiplexer Select 1 1 read-write CTL_FS_MUX_DIS Disable frame sync multiplexing 0 CTL_FS_MUX_EN Enable frame sync multiplexing 1 FSR Frame Sync Required 13 1 read-write CTL_FS_NOT_REQ No frame sync required 0 CTL_FS_REQ Frame sync required 1 GCLKEN Gated Clock Enable 21 1 read-write CTL_GCLK_DIS Disable 0 CTL_GCLK_EN Enable 1 ICLK Internal Clock 10 1 read-write CTL_EXTERNAL_CLK External clock 0 CTL_INTERNAL_CLK Internal clock 1 IFS Internal Frame Sync 14 1 read-write CTL_EXTERNAL_FS External frame sync 0 CTL_INTERNAL_FS Internal frame sync 1 LAFS Late Frame Sync 17 1 read-write CTL_EARLY_FS Early frame sync 0 CTL_LATE_FS Late frame sync 1 LFS Active-Low Frame Sync 16 1 read-write CTL_FS_LO Active high frame sync 0 CTL_FS_HI Active low frame sync 1 LSBF Least-Significant Bit First 3 1 read-write CTL_MSB_FIRST MSB first sent/received 0 CTL_LSB_FIRST LSB first sent/received 1 OPMODE Operation mode 11 1 read-write CTL_SERIAL DSP standard 0 CTL_TIMER_EN_MODE Timer_enable mode 1 PACK Packing Enable 18 2 read-write CTL_PACK_DIS Disable 0 CTL_PACK_8BIT 8-bit packing enable 1 CTL_PACK_16BIT 16-bit packing enable 2 SLEN Serial Word Length 4 5 read-write SPEN Serial Port Enable 0 1 read-write CTL_DIS Disable 0 CTL_EN Enable 1 SPTRAN Serial Port Transfer Direction 25 1 read-write CTL_RX Receive 0 CTL_TX Transmit 1 CTL_B Half SPORT 'B' Control Register 0x40 32 read-write n 0x0 0xFFFFFFFF CKRE Clock Rising Edge 12 1 read-write DIFS Data-Independent Frame Sync 15 1 read-write DMAEN DMA Enable 26 1 read-write FSERRMODE Frame Sync Error Operation 20 1 read-write FSR Frame Sync Required 13 1 read-write GCLKEN Gated Clock Enable 21 1 read-write ICLK Internal Clock 10 1 read-write IFS Internal Frame Sync 14 1 read-write LAFS Late Frame Sync 17 1 read-write LFS Active-Low Frame Sync 16 1 read-write LSBF Least-Significant Bit First 3 1 read-write OPMODE Operation mode 11 1 read-write PACK Packing Enable 18 2 read-write CTL_PACK_DIS Disable 0 CTL_PACK_8BIT 8-bit packing enable 1 CTL_PACK_16BIT 16-bit packing enable 2 SLEN Serial Word Length 4 5 read-write SPEN Serial Port Enable 0 1 read-write SPTRAN Serial Port Transfer Direction 25 1 read-write DIV_A Half SPORT 'A' Divisor Register 0x4 32 read-write n 0x0 0xFFFFFFFF CLKDIV Clock Divisor 0 16 read-write FSDIV Frame Sync Divisor 16 8 read-write DIV_B Half SPORT 'B' Divisor Register 0x44 32 read-write n 0x0 0xFFFFFFFF CLKDIV Clock Divisor 0 16 read-write FSDIV Frame Sync Divisor 16 8 read-write IEN_A Half SPORT A's Interrupt Enable register 0x8 32 read-write n 0x0 0xFFFFFFFF DATA Data request interrupt to the core 3 1 read-write DERRMSK Data Error (Interrupt) Mask 1 1 read-write FSERRMSK Frame Sync Error (Interrupt) Mask 2 1 read-write SYSDATERR Data error for system writes or reads 4 1 read-write TF Transfer Finish Interrupt Enable 0 1 read-write CTL_TXFIN_DIS Transfer finish Interrupt is disabled 0 CTL_TXFIN_EN Transfer Finish Interrupt is Enabled 1 IEN_B Half SPORT B's Interrupt Enable register 0x48 32 read-write n 0x0 0xFFFFFFFF DATA Data request interrupt to the core 3 1 read-write DERRMSK Data Error (Interrupt) Mask 1 1 read-write FSERRMSK Frame Sync Error (Interrupt) Mask 2 1 read-write SYSDATERR Data error for system writes or reads 4 1 read-write TF Transmit Finish Interrupt Enable 0 1 read-write CTL_TXFIN_DIS Transfer Finish Interrupt is disabled 0 CTL_TXFIN_EN Transfer Finish Interrupt is Enabled 1 NUMTRAN_A Half SPORT A Number of transfers register 0x10 32 read-write n 0x0 0xFFFFFFFF VALUE Number of transfers (Half SPORT A) 0 12 read-write NUMTRAN_B Half SPORT B Number of transfers register 0x50 32 read-write n 0x0 0xFFFFFFFF VALUE Number of transfers (Half SPORT B) 0 12 read-write RX_A Half SPORT 'A' Rx Buffer Register 0x28 32 read-write n 0x0 0xFFFFFFFF VALUE Receive Buffer 0 32 read-only RX_B Half SPORT 'B' Rx Buffer Register 0x68 32 read-write n 0x0 0xFFFFFFFF VALUE Receive Buffer 0 32 read-only STAT_A Half SPORT 'A' Status register 0xC 32 read-write n 0x0 0xFFFFFFFF DATA Data Buffer status 3 1 read-only DERR Data Error Status 1 1 read-only DXS Data Transfer Buffer Status 8 2 read-only CTL_EMPTY Empty 0 CTL_PART_FULL Partially full 2 CTL_FULL Full 3 FSERR Frame Sync Error Status 2 1 read-only SYSDATERR System Data Error Status 4 1 read-only TFI Transmit Finish Interrupt Status 0 1 read-only STAT_B Half SPORT 'B' Status register 0x4C 32 read-write n 0x0 0xFFFFFFFF DATA Data Buffer status 3 1 read-only DERR Data Error Status 1 1 read-only DXS Data Transfer Buffer Status 8 2 read-only CTL_EMPTY Empty 0 CTL_PART_FULL Partially full 2 CTL_FULL Full 3 FSERR Frame Sync Error Status 2 1 read-only SYSDATERR System Data Error Status 4 1 read-only TFI Transmit Finish Interrupt Status 0 1 read-only TX_A Half SPORT 'A' Tx Buffer Register 0x20 32 read-write n 0x0 0xFFFFFFFF VALUE Transmit Buffer 0 32 write-only TX_B Half SPORT 'B' Tx Buffer Register 0x60 32 read-write n 0x0 0xFFFFFFFF VALUE Transmit Buffer 0 32 write-only SYS System Identification and Debug Enable SYS 0x40002000 0x0 0x2C registers n SYS_GPIO_INTA GPIO Interrupt A 9 SYS_GPIO_INTB GPIO Interrupt B 10 ADIID ADI Identification 0x20 16 read-write n 0x4144 0xFFFFFFFF VALUE Reads a fixed value of 0x4144 to indicate to debuggers that they are connected to an Analog Devices implemented Cortex based part 0 16 read-only CHIPID Chip Identifier 0x24 16 read-write n 0x2A1 0xFFFFFFFF PARTID Part identifier 4 12 read-only REV Silicon revision 0 4 read-only SWDEN Serial Wire Debug Enable 0x40 16 read-write n 0x7072 0xFFFFFFFF VALUE To enable SWD interface 0 16 write-only TMR0 General Purpose Timer TMR0 0x40000000 0x0 0x40 registers n TMR0_EVT Event 11 ACURCNT 16-bit Timer Value, Asynchronous 0x18 16 read-write n 0x0 0xFFFFFFFF VALUE Counter Value 0 16 read-only ALOAD 16-bit Load Value, Asynchronous 0x14 16 read-write n 0x0 0xFFFFFFFF VALUE Load Value, Asynchronous 0 16 read-write CAPTURE Capture 0x10 16 read-write n 0x0 0xFFFFFFFF VALUE 16-bit Captured Value 0 16 read-only CLRINT Clear Interrupt 0xC 16 read-write n 0x0 0xFFFFFFFF EVTCAPT Clear Captured Event Interrupt 1 1 write-only TIMEOUT Clear Timeout Interrupt 0 1 write-only CTL Control 0x8 16 read-write n 0xA 0xFFFFFFFF CLK Clock Select 5 2 read-write EN Timer Enable 4 1 read-write EVTEN Event Select 13 1 read-write MODE Timer Mode 3 1 read-write PRE Prescaler 0 2 read-write RLD Reload Control 7 1 read-write RSTEN Counter and Prescale Reset Enable 14 1 read-write SYNCBYP Synchronization Bypass 15 1 read-write UP Count up 2 1 read-write CURCNT 16-bit Timer Value 0x4 16 read-write n 0x0 0xFFFFFFFF VALUE Current Count 0 16 read-only EVENTSELECT Timer Event Selection Register 0x28 16 read-write n 0x0 0xFFFFFFFF EVTRANGE Event Select Range 0 6 read-write LOAD 16-bit Load Value 0x0 16 read-write n 0x0 0xFFFFFFFF VALUE Load Value 0 16 read-write PWMCTL PWM Control Register 0x20 16 read-write n 0x0 0xFFFFFFFF IDLESTATE PWM Idle State 1 1 read-write IDLE_LOW PWM idles low 0 IDLE_HIGH PWM idles high 1 MATCH PWM Match Enabled 0 1 read-write PWM_TOGGLE PWM in toggle mode 0 PWM_MATCH PWM in match mode 1 PWMMATCH PWM Match Value 0x24 16 read-write n 0x0 0xFFFFFFFF VALUE PWM Match Value 0 16 read-write STAT Status 0x1C 16 read-write n 0x0 0xFFFFFFFF BUSY Timer Busy 6 1 read-only CAPTURE Capture Event Pending 1 1 read-only CNTRST Counter Reset Occurring 8 1 read-only PDOK Clear Interrupt Register Synchronization 7 1 read-only TIMEOUT Timeout Event Occurred 0 1 read-only TMR1 General Purpose Timer TMR0 0x40000400 0x0 0x40 registers n TMR1_EVT Event 12 ACURCNT 16-bit Timer Value, Asynchronous 0x18 16 read-write n 0x0 0xFFFFFFFF VALUE Counter Value 0 16 read-only ALOAD 16-bit Load Value, Asynchronous 0x14 16 read-write n 0x0 0xFFFFFFFF VALUE Load Value, Asynchronous 0 16 read-write CAPTURE Capture 0x10 16 read-write n 0x0 0xFFFFFFFF VALUE 16-bit Captured Value 0 16 read-only CLRINT Clear Interrupt 0xC 16 read-write n 0x0 0xFFFFFFFF EVTCAPT Clear Captured Event Interrupt 1 1 write-only TIMEOUT Clear Timeout Interrupt 0 1 write-only CTL Control 0x8 16 read-write n 0xA 0xFFFFFFFF CLK Clock Select 5 2 read-write EN Timer Enable 4 1 read-write EVTEN Event Select 13 1 read-write MODE Timer Mode 3 1 read-write PRE Prescaler 0 2 read-write RLD Reload Control 7 1 read-write RSTEN Counter and Prescale Reset Enable 14 1 read-write SYNCBYP Synchronization Bypass 15 1 read-write UP Count up 2 1 read-write CURCNT 16-bit Timer Value 0x4 16 read-write n 0x0 0xFFFFFFFF VALUE Current Count 0 16 read-only EVENTSELECT Timer Event Selection Register 0x28 16 read-write n 0x0 0xFFFFFFFF EVTRANGE Event Select Range 0 6 read-write LOAD 16-bit Load Value 0x0 16 read-write n 0x0 0xFFFFFFFF VALUE Load Value 0 16 read-write PWMCTL PWM Control Register 0x20 16 read-write n 0x0 0xFFFFFFFF IDLESTATE PWM Idle State 1 1 read-write IDLE_LOW PWM idles low 0 IDLE_HIGH PWM idles high 1 MATCH PWM Match Enabled 0 1 read-write PWM_TOGGLE PWM in toggle mode 0 PWM_MATCH PWM in match mode 1 PWMMATCH PWM Match Value 0x24 16 read-write n 0x0 0xFFFFFFFF VALUE PWM Match Value 0 16 read-write STAT Status 0x1C 16 read-write n 0x0 0xFFFFFFFF BUSY Timer Busy 6 1 read-only CAPTURE Capture Event Pending 1 1 read-only CNTRST Counter Reset Occurring 8 1 read-only PDOK Clear Interrupt Register Synchronization 7 1 read-only TIMEOUT Timeout Event Occurred 0 1 read-only TMR2 General Purpose Timer TMR0 0x40000800 0x0 0x40 registers n TMR2_EVT Event 40 ACURCNT 16-bit Timer Value, Asynchronous 0x18 16 read-write n 0x0 0xFFFFFFFF VALUE Counter Value 0 16 read-only ALOAD 16-bit Load Value, Asynchronous 0x14 16 read-write n 0x0 0xFFFFFFFF VALUE Load Value, Asynchronous 0 16 read-write CAPTURE Capture 0x10 16 read-write n 0x0 0xFFFFFFFF VALUE 16-bit Captured Value 0 16 read-only CLRINT Clear Interrupt 0xC 16 read-write n 0x0 0xFFFFFFFF EVTCAPT Clear Captured Event Interrupt 1 1 write-only TIMEOUT Clear Timeout Interrupt 0 1 write-only CTL Control 0x8 16 read-write n 0xA 0xFFFFFFFF CLK Clock Select 5 2 read-write EN Timer Enable 4 1 read-write EVTEN Event Select 13 1 read-write MODE Timer Mode 3 1 read-write PRE Prescaler 0 2 read-write RLD Reload Control 7 1 read-write RSTEN Counter and Prescale Reset Enable 14 1 read-write SYNCBYP Synchronization Bypass 15 1 read-write UP Count up 2 1 read-write CURCNT 16-bit Timer Value 0x4 16 read-write n 0x0 0xFFFFFFFF VALUE Current Count 0 16 read-only EVENTSELECT Timer Event Selection Register 0x28 16 read-write n 0x0 0xFFFFFFFF EVTRANGE Event Select Range 0 6 read-write LOAD 16-bit Load Value 0x0 16 read-write n 0x0 0xFFFFFFFF VALUE Load Value 0 16 read-write PWMCTL PWM Control Register 0x20 16 read-write n 0x0 0xFFFFFFFF IDLESTATE PWM Idle State 1 1 read-write IDLE_LOW PWM idles low 0 IDLE_HIGH PWM idles high 1 MATCH PWM Match Enabled 0 1 read-write PWM_TOGGLE PWM in toggle mode 0 PWM_MATCH PWM in match mode 1 PWMMATCH PWM Match Value 0x24 16 read-write n 0x0 0xFFFFFFFF VALUE PWM Match Value 0 16 read-write STAT Status 0x1C 16 read-write n 0x0 0xFFFFFFFF BUSY Timer Busy 6 1 read-only CAPTURE Capture Event Pending 1 1 read-only CNTRST Counter Reset Occurring 8 1 read-only PDOK Clear Interrupt Register Synchronization 7 1 read-only TIMEOUT Timeout Event Occurred 0 1 read-only TMR_RGB Timer_RGB with 3 PWM outputs TMR_RGB 0x40000C00 0x0 0x40 registers n TMR_RGB_EVT Event 69 ACURCNT 16-bit timer value, asynchronous 0x18 16 read-write n 0x0 0xFFFFFFFF VALUE Counter value 0 16 read-only ALOAD 16-bit load value, asynchronous 0x14 16 read-write n 0x0 0xFFFFFFFF VALUE Load value, asynchronous 0 16 read-write CAPTURE Capture 0x10 16 read-write n 0x0 0xFFFFFFFF VALUE 16-bit captured value 0 16 read-only CLRINT Clear interrupt 0xC 16 read-write n 0x0 0xFFFFFFFF EVTCAPT Clear captured event interrupt 1 1 write-only TIMEOUT Clear timeout interrupt 0 1 write-only CTL Control 0x8 16 read-write n 0xA 0xFFFFFFFF CLK Clock select 5 2 read-write EN Timer enable 4 1 read-write EVTEN Event select 13 1 read-write MODE Timer mode 3 1 read-write PRE Prescaler 0 2 read-write RLD Reload control 7 1 read-write RSTEN Counter and prescale reset enable 14 1 read-write SYNCBYP Synchronization bypass 15 1 read-write UP Count up 2 1 read-write CURCNT 16-bit timer value 0x4 16 read-write n 0x0 0xFFFFFFFF VALUE Current count 0 16 read-only EVENTSELECT Timer Event selection Register 0x28 16 read-write n 0x0 0xFFFFFFFF EVTRANGE Event select range 0 6 read-write LOAD 16-bit load value 0x0 16 read-write n 0x0 0xFFFFFFFF VALUE Load value 0 16 read-write PWM0CTL PWM0 Control Register 0x20 16 read-write n 0x0 0xFFFFFFFF IDLESTATE PWM Idle State 1 1 read-write MATCH PWM Match enabled 0 1 read-write PWM0MATCH PWM0 Match Value 0x24 16 read-write n 0x0 0xFFFFFFFF VALUE PWM Match Value 0 16 read-write PWM1CTL PWM1 Control Register 0x2C 16 read-write n 0x0 0xFFFFFFFF IDLESTATE PWM Idle State 1 1 read-write MATCH PWM Match enabled 0 1 read-write PWM1MATCH PWM1 Match Value 0x30 16 read-write n 0x0 0xFFFFFFFF VALUE PWM Match Value 0 16 read-write PWM2CTL PWM2 Control Register 0x34 16 read-write n 0x0 0xFFFFFFFF IDLESTATE PWM Idle State 1 1 read-write MATCH PWM Match enabled 0 1 read-write PWM2MATCH PWM2 Match Value 0x38 16 read-write n 0x0 0xFFFFFFFF VALUE PWM Match Value 0 16 read-write STAT Status 0x1C 16 read-write n 0x0 0xFFFFFFFF BUSY Timer Busy 6 1 read-only CAPTURE Capture event pending 1 1 read-only CNTRST Counter reset occurring 8 1 read-only PDOK Clear Interrupt Register synchronization 7 1 read-only TIMEOUT Timeout event occurred 0 1 read-only UART0 Universal Asynchronous Receiver/Transmitter UART0 0x40005000 0x0 0x100 registers n UART0_EVT UART0 Event 14 ACR Auto Baud Control 0x40 16 read-write n 0x0 0xFFFFFFFF ABE Auto Baud Enable 0 1 read-write DIS_AUTOBAUD Disable auto baudrate 0 EN_AUTOBAUD Enable auto baudrate 1 DNIEN Enable Done Interrupt 1 1 read-write DIS_DONEINT Disable done interrupt 0 EN_DONEINT Enable done interrupt 1 EEC Ending Edge Count 8 4 read-write EEC_EDGE1 First edge 0 EEC_EDGE2 Second edge 1 EEC_EDGE3 Third edge 2 EEC_EDGE4 Fourth edge 3 EEC_EDGE5 Fifth edge 4 EEC_EDGE6 Sixth edge 5 EEC_EDGE7 Seventh edge 6 EEC_EDGE8 Eighth edge 7 EEC_EDGE9 Ninth edge 8 SEC Starting Edge Count 4 3 read-write SEC_EDGE1 First edge 0 SEC_EDGE2 Second edge 1 SEC_EDGE3 Third edge 2 SEC_EDGE4 Fourth edge 3 SEC_EDGE5 Fifth edge 4 SEC_EDGE6 Sixth edge 5 SEC_EDGE7 Seventh edge 6 SEC_EDGE8 Eighth edge 7 TOIEN Enable Time-out Interrupt 2 1 read-write DIS_TIMEOUTINT Disable timeout interrupt 0 EN_TIMEOUTINT Enable timeout interrupt 1 ASRH Auto Baud Status (High) 0x48 16 read-write n 0x0 0xFFFFFFFF CNT CNT[19:12] Auto Baud Counter Value 0 8 read-only ASRL Auto Baud Status (Low) 0x44 16 read-write n 0x0 0xFFFFFFFF BRKTO Timed Out Due to Long Time Break Condition 1 1 read-only CNT CNT[11:0] Auto Baud Counter Value 4 12 read-only DONE Auto Baud Done Successfully 0 1 read-only NEETO Timed Out Due to No Valid Ending Edge Found 3 1 read-only NSETO Timed Out Due to No Valid Start Edge Found 2 1 read-only CTL UART Control Register 0x30 16 read-write n 0x100 0xFFFFFFFF FORCECLK Force UCLK on 1 1 read-write REV UART Revision ID 8 8 read-only RXINV Invert Receiver Line 4 1 read-write NOTINV_RX Don't invert receiver line (idling high). 0 INV_RX Invert receiver line (idling low). 1 DIV Baud Rate Divider 0x28 16 read-write n 0x0 0xFFFFFFFF DIV Baud Rate Divider 0 16 read-write FBR Fractional Baud Rate 0x24 16 read-write n 0x0 0xFFFFFFFF DIVM Fractional Baud Rate M Divide Bits 1 to 3 11 2 read-write DIVN Fractional Baud Rate N Divide Bits 0 to 2047 0 11 read-write FBEN Fractional Baud Rate Generator Enable 15 1 read-write FCR FIFO Control 0x20 16 read-write n 0x0 0xFFFFFFFF FDMAMD FIFO DMA Mode 3 1 read-write MODE0 In DMA mode 0, RX DMA request will be asserted whenever there's data in RBR or RX FIFO and de-assert whenever RBR or RX FIFO is empty TX DMA request will be asserted whenever THR or TX FIFO is empty and de-assert whenever data written to. 0 MODE1 in DMA mode 1, RX DMA request will be asserted whenever RX FIFO trig level or time out reached and de-assert thereafter when RX FIFO is empty TX DMA request will be asserted whenever TX FIFO is empty and de-assert thereafter when TX FIFO is completely filled up full. 1 FIFOEN FIFO Enable as to Work in 16550 Mode 0 1 read-write RFCLR Clear Rx FIFO 1 1 write-only RFTRIG Rx FIFO Trigger Level 6 2 read-write TFCLR Clear Tx FIFO 2 1 write-only IEN Interrupt Enable 0x4 16 read-write n 0x0 0xFFFFFFFF EDMAR DMA Requests in Receive Mode 5 1 read-write EDMAT DMA Requests in Transmit Mode 4 1 read-write EDSSI Modem Status Interrupt 3 1 read-write ELSI Rx Status Interrupt 2 1 read-write ERBFI Receive Buffer Full Interrupt 0 1 read-write ETBEI Transmit Buffer Empty Interrupt 1 1 read-write IIR Interrupt ID 0x8 16 read-write n 0x1 0xFFFFFFFF FEND FIFO Enabled 6 2 read-only NIRQ Interrupt Flag 0 1 read-only STAT Interrupt Status 1 3 read-only STAT_EDSSI Modem status interrupt (Read MSR register to clear) 0 STAT_ETBEI Transmit buffer empty interrupt (Write to Tx register or read IIR register to clear) 1 STAT_ERBFI Receive buffer full interrupt (Read Rx register to clear) 2 STAT_RLSI Receive line status interrupt (Read LSR register to clear) 3 STAT_RFTOI Receive FIFO time-out interrupt (Read Rx register to clear) 6 LCR Line Control 0xC 16 read-write n 0x0 0xFFFFFFFF BRK Set Break 6 1 read-write EPS Parity Select 4 1 read-write PEN Parity Enable 3 1 read-write SP Stick Parity 5 1 read-write PAR_NOTFORCED Parity will not be forced based on Parity Select and Parity Enable bits. 0 PAR_FORCED Parity forced based on Parity Select and Parity Enable bits. 1 STOP Stop Bit 2 1 read-write WLS Word Length Select 0 2 read-write LCR2 Second Line Control 0x2C 16 read-write n 0x2 0xFFFFFFFF OSR Over Sample Rate 0 2 read-write LSR Line Status 0x14 16 read-write n 0x60 0xFFFFFFFF BI Break Indicator 4 1 read-only DR Data Ready 0 1 read-only FE Framing Error 3 1 read-only FIFOERR Rx FIFO Parity Error/Frame Error/Break Indication 7 1 read-only OE Overrun Error 1 1 read-only PE Parity Error 2 1 read-only TEMT Transmit and Shift Register Empty Status 6 1 read-only THRE Transmit Register Empty 5 1 read-only MCR Modem Control 0x10 16 read-write n 0x0 0xFFFFFFFF DTR Data Terminal Ready 0 1 read-write LOOPBACK Loopback Mode 4 1 read-write OUT1 Output 1 2 1 read-write OUT2 Output 2 3 1 read-write RTS Request to Send 1 1 read-write MSR Modem Status 0x18 16 read-write n 0x0 0xFFFFFFFF CTS Clear to Send 4 1 read-only DCD Data Carrier Detect 7 1 read-only DCTS Delta CTS 0 1 read-only DDCD Delta DCD 3 1 read-only DDSR Delta DSR 1 1 read-only DSR Data Set Ready 5 1 read-only RI Ring Indicator 6 1 read-only TERI Trailing Edge RI 2 1 read-only RFC RX FIFO Byte Count 0x34 16 read-write n 0x0 0xFFFFFFFF RFC Current Rx FIFO Data Bytes 0 5 read-only RSC RS485 Half-duplex Control 0x3C 16 read-write n 0x0 0xFFFFFFFF DISRX Disable Rx When Transmitting 2 1 read-write DISTX Hold off Tx When Receiving 3 1 read-write OENP SOUT_EN Polarity 0 1 read-write OENSP SOUT_EN De-assert Before Full Stop Bit(s) 1 1 read-write RX Receive Buffer Register 0x0 16 read-write n 0x0 0xFFFFFFFF RBR Receive Buffer Register 0 8 read-only SCR Scratch Buffer 0x1C 16 read-write n 0x0 0xFFFFFFFF SCR Scratch 0 8 read-write TFC TX FIFO Byte Count 0x38 16 read-write n 0x0 0xFFFFFFFF TFC Current Tx FIFO Data Bytes 0 5 read-only TX Transmit Holding Register RX 0x0 16 read-write n 0x0 0xFFFFFFFF THR Transmit Holding Register 0 8 write-only UART1 Universal Asynchronous Receiver/Transmitter UART0 0x40005400 0x0 0x100 registers n UART1_EVT Event 66 ACR Auto Baud Control 0x40 16 read-write n 0x0 0xFFFFFFFF ABE Auto Baud Enable 0 1 read-write DIS_AUTOBAUD Disable auto baudrate 0 EN_AUTOBAUD Enable auto baudrate 1 DNIEN Enable Done Interrupt 1 1 read-write DIS_DONEINT Disable done interrupt 0 EN_DONEINT Enable done interrupt 1 EEC Ending Edge Count 8 4 read-write EEC_EDGE1 First edge 0 EEC_EDGE2 Second edge 1 EEC_EDGE3 Third edge 2 EEC_EDGE4 Fourth edge 3 EEC_EDGE5 Fifth edge 4 EEC_EDGE6 Sixth edge 5 EEC_EDGE7 Seventh edge 6 EEC_EDGE8 Eighth edge 7 EEC_EDGE9 Ninth edge 8 SEC Starting Edge Count 4 3 read-write SEC_EDGE1 First edge 0 SEC_EDGE2 Second edge 1 SEC_EDGE3 Third edge 2 SEC_EDGE4 Fourth edge 3 SEC_EDGE5 Fifth edge 4 SEC_EDGE6 Sixth edge 5 SEC_EDGE7 Seventh edge 6 SEC_EDGE8 Eighth edge 7 TOIEN Enable Time-out Interrupt 2 1 read-write DIS_TIMEOUTINT Disable timeout interrupt 0 EN_TIMEOUTINT Enable timeout interrupt 1 ASRH Auto Baud Status (High) 0x48 16 read-write n 0x0 0xFFFFFFFF CNT CNT[19:12] Auto Baud Counter Value 0 8 read-only ASRL Auto Baud Status (Low) 0x44 16 read-write n 0x0 0xFFFFFFFF BRKTO Timed Out Due to Long Time Break Condition 1 1 read-only CNT CNT[11:0] Auto Baud Counter Value 4 12 read-only DONE Auto Baud Done Successfully 0 1 read-only NEETO Timed Out Due to No Valid Ending Edge Found 3 1 read-only NSETO Timed Out Due to No Valid Start Edge Found 2 1 read-only CTL UART Control Register 0x30 16 read-write n 0x100 0xFFFFFFFF FORCECLK Force UCLK on 1 1 read-write REV UART Revision ID 8 8 read-only RXINV Invert Receiver Line 4 1 read-write NOTINV_RX Don't invert receiver line (idling high). 0 INV_RX Invert receiver line (idling low). 1 DIV Baud Rate Divider 0x28 16 read-write n 0x0 0xFFFFFFFF DIV Baud Rate Divider 0 16 read-write FBR Fractional Baud Rate 0x24 16 read-write n 0x0 0xFFFFFFFF DIVM Fractional Baud Rate M Divide Bits 1 to 3 11 2 read-write DIVN Fractional Baud Rate N Divide Bits 0 to 2047 0 11 read-write FBEN Fractional Baud Rate Generator Enable 15 1 read-write FCR FIFO Control 0x20 16 read-write n 0x0 0xFFFFFFFF FDMAMD FIFO DMA Mode 3 1 read-write MODE0 In DMA mode 0, RX DMA request will be asserted whenever there's data in RBR or RX FIFO and de-assert whenever RBR or RX FIFO is empty TX DMA request will be asserted whenever THR or TX FIFO is empty and de-assert whenever data written to. 0 MODE1 in DMA mode 1, RX DMA request will be asserted whenever RX FIFO trig level or time out reached and de-assert thereafter when RX FIFO is empty TX DMA request will be asserted whenever TX FIFO is empty and de-assert thereafter when TX FIFO is completely filled up full. 1 FIFOEN FIFO Enable as to Work in 16550 Mode 0 1 read-write RFCLR Clear Rx FIFO 1 1 write-only RFTRIG Rx FIFO Trigger Level 6 2 read-write TFCLR Clear Tx FIFO 2 1 write-only IEN Interrupt Enable 0x4 16 read-write n 0x0 0xFFFFFFFF EDMAR DMA Requests in Receive Mode 5 1 read-write EDMAT DMA Requests in Transmit Mode 4 1 read-write EDSSI Modem Status Interrupt 3 1 read-write ELSI Rx Status Interrupt 2 1 read-write ERBFI Receive Buffer Full Interrupt 0 1 read-write ETBEI Transmit Buffer Empty Interrupt 1 1 read-write IIR Interrupt ID 0x8 16 read-write n 0x1 0xFFFFFFFF FEND FIFO Enabled 6 2 read-only NIRQ Interrupt Flag 0 1 read-only STAT Interrupt Status 1 3 read-only STAT_EDSSI Modem status interrupt (Read MSR register to clear) 0 STAT_ETBEI Transmit buffer empty interrupt (Write to Tx register or read IIR register to clear) 1 STAT_ERBFI Receive buffer full interrupt (Read Rx register to clear) 2 STAT_RLSI Receive line status interrupt (Read LSR register to clear) 3 STAT_RFTOI Receive FIFO time-out interrupt (Read Rx register to clear) 6 LCR Line Control 0xC 16 read-write n 0x0 0xFFFFFFFF BRK Set Break 6 1 read-write EPS Parity Select 4 1 read-write PEN Parity Enable 3 1 read-write SP Stick Parity 5 1 read-write PAR_NOTFORCED Parity will not be forced based on Parity Select and Parity Enable bits. 0 PAR_FORCED Parity forced based on Parity Select and Parity Enable bits. 1 STOP Stop Bit 2 1 read-write WLS Word Length Select 0 2 read-write LCR2 Second Line Control 0x2C 16 read-write n 0x2 0xFFFFFFFF OSR Over Sample Rate 0 2 read-write LSR Line Status 0x14 16 read-write n 0x60 0xFFFFFFFF BI Break Indicator 4 1 read-only DR Data Ready 0 1 read-only FE Framing Error 3 1 read-only FIFOERR Rx FIFO Parity Error/Frame Error/Break Indication 7 1 read-only OE Overrun Error 1 1 read-only PE Parity Error 2 1 read-only TEMT Transmit and Shift Register Empty Status 6 1 read-only THRE Transmit Register Empty 5 1 read-only MCR Modem Control 0x10 16 read-write n 0x0 0xFFFFFFFF DTR Data Terminal Ready 0 1 read-write LOOPBACK Loopback Mode 4 1 read-write OUT1 Output 1 2 1 read-write OUT2 Output 2 3 1 read-write RTS Request to Send 1 1 read-write MSR Modem Status 0x18 16 read-write n 0x0 0xFFFFFFFF CTS Clear to Send 4 1 read-only DCD Data Carrier Detect 7 1 read-only DCTS Delta CTS 0 1 read-only DDCD Delta DCD 3 1 read-only DDSR Delta DSR 1 1 read-only DSR Data Set Ready 5 1 read-only RI Ring Indicator 6 1 read-only TERI Trailing Edge RI 2 1 read-only RFC RX FIFO Byte Count 0x34 16 read-write n 0x0 0xFFFFFFFF RFC Current Rx FIFO Data Bytes 0 5 read-only RSC RS485 Half-duplex Control 0x3C 16 read-write n 0x0 0xFFFFFFFF DISRX Disable Rx When Transmitting 2 1 read-write DISTX Hold off Tx When Receiving 3 1 read-write OENP SOUT_EN Polarity 0 1 read-write OENSP SOUT_EN De-assert Before Full Stop Bit(s) 1 1 read-write RX Receive Buffer Register 0x0 16 read-write n 0x0 0xFFFFFFFF RBR Receive Buffer Register 0 8 read-only SCR Scratch Buffer 0x1C 16 read-write n 0x0 0xFFFFFFFF SCR Scratch 0 8 read-write TFC TX FIFO Byte Count 0x38 16 read-write n 0x0 0xFFFFFFFF TFC Current Tx FIFO Data Bytes 0 5 read-only TX Transmit Holding Register RX 0x0 16 read-write n 0x0 0xFFFFFFFF THR Transmit Holding Register 0 8 write-only WDT0 Watchdog Timer WDT0 0x40002C00 0x0 0x20 registers n WDT_EXP Expiration 5 CCNT Current Count Value 0x4 16 read-write n 0x1000 0xFFFFFFFF VALUE Current Count Value 0 16 read-only CTL Control 0x8 16 read-write n 0xE9 0xFFFFFFFF EN Timer Enable 5 1 read-write WDT_DIS WDT not enabled 0 WDT_EN WDT enabled 1 IRQ Timer Interrupt 1 1 read-write RST WDT asserts reset when timed out 0 INT WDT generates interrupt when timed out 1 MODE Timer Mode 6 1 read-write FREE_RUN Free running mode 0 PERIODIC Periodic mode 1 PRE Prescaler 2 2 read-write div1 Source clock/1 0 div16 Source clock/16 1 div256 Source clock/256 (default) 2 SPARE Unused Spare Bit 7 1 read-write LOAD Load Value 0x0 16 read-write n 0x1000 0xFFFFFFFF VALUE Load Value 0 16 read-write RESTART Clear Interrupt 0xC 16 read-write n 0x0 0xFFFFFFFF CLRWORD Clear Watchdog 0 16 write-only STAT Status 0x18 16 read-write n 0x0 0xFFFFFFFF CLRIRQ Clear Interrupt Register Write Sync in Progress 1 1 read-only COUNTING Control Register Write Sync in Progress 3 1 read-only COUNT_MATCH APB and WDT clock domain CTRL values match 0 COUNT_SYNCING APB CTRL register values are being synchronized to WDT clock domain. 1 IRQ WDT Interrupt 0 1 read-only LOADING Load Register Write Sync in Progress 2 1 read-only LOAD_MATCH APB and WDT clock domains LOAD values match. 0 LOAD_SYNCING APB LOAD value is being synchronized to WDT clock domain. 1 LOCKED Lock Status Bit 4 1 read-only XINT0 External interrupt configuration XINT0 0x4004C080 0x0 0x50 registers n XINT_EVT0 External Wakeup Interrupt n 1 XINT_EVT1 External Wakeup Interrupt n 2 XINT_EVT2 External Wakeup Interrupt n 3 XINT_EVT3 External Wakeup Interrupt n 4 CFG0 External Interrupt Configuration 0x0 32 read-write n 0x200000 0xFFFFFFFF IRQ0EN External Interrupt 0 Enable 3 1 read-write IRQ0MDE External Interrupt 0 Mode Registers 0 3 read-write IRQ1EN External Interrupt 1 Enable 7 1 read-write IRQ1MDE External Interrupt 1 Mode Registers 4 3 read-write IRQ2EN External Interrupt 2 Enable 11 1 read-write IRQ2MDE External Interrupt 2 Mode Registers 8 3 read-write IRQ3EN External Interrupt 3 Enable 15 1 read-write IRQ3MDE External Interrupt 3 Mode Registers 12 3 read-write UART_RX_EN External Interrupt Using UART_RX Enable Bit 20 1 read-write UART_RX_MDE External Interrupt Using UART_RX Wakeup Mode Registers 21 3 read-write CLR External Interrupt Clear 0x10 32 read-write n 0x0 0xFFFFFFFF IRQ0 External Interrupt 0 0 1 read-write IRQ1 External Interrupt 1 1 1 read-write IRQ2 External Interrupt 2 2 1 read-write IRQ3 External Interrupt 3 3 1 read-write UART_RX_CLR External Interrupt Clear for UART_RX WAKEUP Interrupt 5 1 read-write EXT_STAT External Wakeup Interrupt Status 0x4 32 read-write n 0x0 0xFFFFFFFF STAT_EXTINT0 Interrupt Status Bit for External Interrupt 0 0 1 read-only STAT_EXTINT1 Interrupt Status Bit for External Interrupt 1 1 1 read-only STAT_EXTINT2 Interrupt Status Bit for External Interrupt 2 2 1 read-only STAT_EXTINT3 Interrupt Status Bit for External Interrupt 3 3 1 read-only STAT_UART_RXWKUP Interrupt Status Bit for UART RX WAKEUP Interrupt 5 1 read-only NMICLR Non-maskable Interrupt Clear 0x14 32 read-write n 0x0 0xFFFFFFFF CLR NMI Clear 0 1 read-write